Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters

Abstract

In this article, a synchronous rotating-frame based phase-locked loop (PLL) for a single-phase PV inverter control system is presented. Detailed PLL mathematical model and the digital implementation for a single-phase PV inverter system are presented. A practical solution for transport delay based orthogonal signal generation using first-in-first-out (FIFO) circular buffer is also discussed. Details of implementation for a real-time system using digital signal processor were also described. The performance of the developed PLL was experimentally verified on a developed single-phase PV inverter prototype.

Keywords:

• single-phase PLL
• orthogonal signal generator
• PI controller
• single-phase PV inverter

Additional information

Notes on contributors

Zhongfu Zhou

Zhongfu Zhou received the Ph.D. degree in Power Electronics from Sussex University, UK in 2004 then he joined Swansea University as a research officer. Presently, he is a lecturer in power electronics in the college of engineering at Swansea university, UK. His current research interests are in power electronics converters and real-time control for solar and wave power conversion systems, active power filter, active front-end rectifier, electrical machine control as well as power systems. He has published over 50 scientific papers in various international journals and conferences.