Ultra-low-power and compact 8-bit CMOS priority encoder

ABSTRACT

An ultra-low-power, 55-transistor 8-bit priority encoder is proposed, based on a modified n-type dynamic scheme using feedback from higher- to lower-priority outputs. A comparative study, including other designs from literature, is performed on transistor level at 32 and 45 nm predictive technology. The simulation results showed that, compared to the other examined works, the proposed circuit achieves reduction in power dissipation as high as 88% and reduction in power delay product, up to 93.0% while having the smallest transistor count. It is thus proved to be an all-around efficient design in terms of power, performance and area.

KEYWORDS:

• Priority encoder
• low-power
• CMOS

Disclosure statement

No potential conflict of interest was reported by the authors.