Truncation Based Approximate Multiplier For Error Resilient Applications

ABSTRACT

Approximate computing is a promising approach for low power IC design and has recently received considerable research attention. To accommodate dynamic levels of approximation, a few accuracy configurable multiplier designs have been developed in the past. However, these designs consumed considerable area and power. Accuracy, as well as latency, power and area design metrics are used to evaluate our approximate multiplier designs of different bit widths, i.e. 16 x 16, 32 × 32 and 64 × 64. Simulation and synthesis results showed a considerable gain than previous designs since we can change the components required according to the error tolerance. Moreover, we have also proposed a technique, where the system takes charge of the design and makes a call depending on the magnitude of the numbers provided. When compared with the exact multiplier designs, for 16 bit, 32 bit and 64 bit, we achieved a reduction by 24.5%, 71.5% and 85.1% in area; reduction in power by 37.7%, 89.4% and 88.2% and with a mean relative error distance of 0.5393%, 0.5428% and 0.2878% respectively.

KEYWORDS:

• Approximate multiplier
• dynamic approximation
• error tolerant system
• latency parameter
• truncation

Disclosure statement

No potential conflict of interest was reported by the author(s).