Power optimisation of single phase clocked feedback D flip-flop for CDMA

ABSTRACT

A low power flip-flop is demanding delay element in digital sigma delta modulator of DAC system. This paper highlights power optimisation of single-phase clocked feedback D flip-flop using various optimisation techniques like clock gating, MTCMOS etc. In this scenario, clock gating using GDI and single-phase clocked inverter is invented to avoid unwanted no data transitions of flip-flop, also proposed type is compared with existing techniques. In addition to this, full swing GDI (gate-Diffusion Input) cell itself is modified by single phase clocked inverter to minimise threshold voltage drop and unwanted spikes at the output. There is trade off in area, speed and power. This work is based on power optimisation with favourable speed and area. Flip-flop is verified for clock frequency of 50 MHz as well as CDMA (Code Division Multiple Access) frequency of 1.6 MHz. Analysis is carried out in SPECTRE simulator of CADENCE environment with 180 nm technology supplied by AMS. Not only power but delay is also measured to check the performance of flip-flop. Proposed circuit gives 92.8% power and power delay product improvement.

KEYWORDS:

• Power
• flip-flop
• optimisation
• clock-gating
• MTCMOS

Disclosure statement

No potential conflict of interest was reported by the author(s).