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Research Article

A detection for patent infringement suit via nanotopology induced by graph

, & | (Reviewing Editor)
Article: 1161129 | Received 08 Oct 2015, Accepted 26 Feb 2016, Published online: 18 Apr 2016

Abstract

The aim of this paper was to generate nanotopological structure on the power set of vertices of simple digraphs using new definition neighbourhood of vertices on out linked of digraphs. Based on the neighbourhood we define the approximations of the subgraphs of a graph. A new nanotopological graph reduction to symbolic circuit analysis is developed in this paper. By means of structural equivalence on nanotopology induced by graph we have framed an algorithm for detecting patent infringement suit.

2010 AMS Subject classifications:

Public Interest Statement

Lellis Thivagar introduced nanotopological space with respect to a subset X of an universe which is defined in terms of lower and upper approximations of X. The elements of a nanotopological space are called the nano-open sets. But certain nanoterms are satisfied simply to mean “very small”. It originates from the Greek word “Nanos” which means “Dwarf” in its modern scientific sense, an order to magnititude—one billionth of something. Nanocar is an example. The topology recommended here is named so because of its size, since it has atmost five elements in it. The purpose of the present work was to put a starting point for the nanotopological graph theory. We hope these new results will further assist to comprehend the concept of nanotopological space in various applied fields.

1. Introduction

The theory of nanotopology proposed by Lellis Thivagar and Richard (Citation2013a, Citationb), is an extension of set theory for the study of intelligent systems characterized by in sufficient and incomplete information. The purpose of the present work was to put a starting point for the nanotopological graph theory. Most real-life situations need some sort of approximation to fit mathematical models. The beauty of using nanotopology in approximation is achieved via approximation for qualitative subgraphs without coding or using assumption. We believe that nanotopological graph structure will be an important base for modification of knowledge extraction of processing. In this section, we define graphical isomorphism (Diestel, Diestel (Citation2010); Jensen & Shen, Citation2007) is a related task for deciding when two graphs with different specifications are structurally equivalent, that is whether they have the same pattern of connections. Nanohomeomorphism (Bonikowski, Bryniarski, & Wybraniec, Citation1998) between two nanotopological spaces are said to be topologically equivalent. Here, we are formalizing the structural equivalence of basic circuit of the chips from the graphs and their corresponding nanotopologies generated by them.

2. Preliminaries

This section represents a review of some fundamental notions related to nanotopology and graph theory.

Definition 2.1

   (Lellis Thivagar & Richard, Citation2013a, Citationb) Let U be an universe. R be an equivalence relation on U and τR(X)={U,,LR(X),UR(X),BR(X)} where XU. τR(X) satisfies the following axioms:

(i)

U and τR(X).

(ii)

The union of elements of any sub collection of τR(X) is in τR(X).

(iii)

The intersection of the elements of any finite sub collection of τR(X) is in τR(X). That is, τR(X) forms a topology on U the nanotopology on U with respect to X. We call (U,τR(X)) as the nanotopological space. The elements of τR(X) are called nano-open sets.

Definition 2.2

(Bonikowski et al., Citation1998; Diestel, Diestel (Citation2010)) A graph G is an ordered pair of disjoint sets (VE), where V is nonempty and E is a subset of unordered pairs of V. The vertices and edges of a graph G are the elements of V=V(G) and E=E(G), respectively. We say that a graph G is finite (resp. infinite) if the set V(G) is finite (resp.finite). The degree of a vertex uV(G) is the number of edge in a graph contains a vertex u, then u is called an isolated point and so the degree of u is zero (Lellis Thivagar & Richard, Citation2013a, Citationb). An edge which has the same vertex to ends is called a loop and the edge with distinct ends is called a link (Jensen & Shen, Citation2007).

Definition 2.3

(Bonikowski et al., Citation1998; Diestel, Diestel (Citation2010)) A graph is simple if it has no loops and no two of its links join the same pair of vertices. A graph which has no edge called a null graph. A graph which has no vertices is called a empty graph (Jensen & Shen, Citation2007; Lellis Thivagar & Richard, Citation2013a, Citationb).

Definition 2.4

(Deseor & Kuh, Citation2009; Diestel, Diestel (Citation2010)) If G[V, E] is a directed graph and u,vV, then:

(i)

u is invertex of v if uvE(G).

(ii)

u is outvertex of v if vuE(G).

(iii)

The indegree of a vertex ’v’ is the number of vertices ’u’ such that uvE(G).

(iv)

The outdegree of a vertex ’v’ is the number of vertices ’u’ such that vuE(G).

Throughout this paper the word graph means direct simple graph.

3. Approximations via neighbourhood

In this section, we will define lower and upper approximation of subgraph H of a graph G[V, E]. Some properties of these concepts are studied.

Definition 3.1

Let G(V,E) be a graph, vV(G). Then we define the neighbourhood of ’v’ as follows, N(v)={v}{uV(G):vuE(G)}.

Definition 3.2

Let G(V,E) be a graph, H is a subgraph of G and N(v) be neighbourhood of v in V. Then we define

(i)

The lower approximation operation as follows: L:P[V(G)]P[V(G)] such that, LN[V(H)]=vV(G){v|N(v)V(H)}

(ii)

The upper approximation operation as follows: U:P[V(G)]P[V(G)] such that, UN[V(H)]={N(v):vV(H)}

(iii)

The boundary region is defined as BN[V(H)]=UN[V(H)]-LN[V(H)]

Definition 3.3

Let G be a graph, N(v) be neighbourhood of v in V and H be a subgraph of G, τN[V(H)]={V(G),,LN[V(H)],UN[V(H)],BN[V(H)]} forms a topolgy on V(G) called the nanotopology on V(G) with respect to V(H). We call [V(G),τN[V(H)]] as the nanotopological space induced by a graph.

Example 3.4

Consider Figure .

Then V(G)={V1,V2,V3,V4} and N(v1)={V1,V2,V3},N(v2)={v1,v2,v3},N(v3)={v3},N(v4)={v3,v4} and H be a subgraph of G, where V(H)={V2,V3,V4}, then LN[V(H)]={V3,V4},UN[V(H)]=V(G),BN[V(H)]={V1,V2}. Therefore, the nanotopology induced by the graph is τN[V(H)]={V(G),,{V3,V4},{V1,V2}} and let H be a subgraph of G, where V(H)={V1,V2} then LN[V(H)]={V3},UN[V(H)]={V1,V2,V3},BN[V(H)]={V1,V2}. Therefore, the nanotopology induced by the graph is τN[V(H)]={V(G),,{V3},{V1,V2,V3},{V1,V2}}

Figure 1. Graph for Example 3.4.

Figure 1. Graph for Example 3.4.

Theorem 3.5

Let G[V, E] be a graph, H is a subgraph of G, then:

(i)

LN[V(H)]V(H)UN[V(H)]

(ii)

LN[V(G)]=V(G)=UN[V(G)]

(iii)

LN[]=UN[]=.

Theorem 3.6

Let G[V, E] be a graph, H and K are two subgraphs of a graph G, then

(a)

If V(H)V(K) then LN[V(H)]LN[V(K)] and UN[V(H)]UN[V(K)]

(b)

LN[V(H)]LN[V(K)]LN[V(H)V(K)]

(c)

LN[V(H)V(K)]=LN[V(H)]LN[V(K)]

(d)

UN[V(H)V(K)]=UN[V(H)]UN[V(K)]

(e)

UN[V(H)V(K)]UN[V(H)]UN[V(K)]

Proof

 

(a)

Let vLN[V(H)]. By definition of LN[V(H)], N(v)V(H), but V(H)V(K)N(v)V(H)V(K) and hence vLN[V(K)]. Since vLN[V(H)]vLN[V(K)]. Therefore LN[V(H)]LN[V(K)]. In a similar manner we can also prove that UN[V(H)]UN[V(K)].

(b)

Since V[H]V(H)V(K),V[K]V(H)V(K),LN[V(H)]LN[V(H)V(K)],andLN[V(K)]LN[V(H)V(K)]. Therefore LN[V(H)]LN[V(K)]LN[V(H)V(K)].

(c)

Since V(H)V(K)V(H),V(H)V(K)V(K),LN[V(H)V(K)]LN[V(H)] and LN[V(H)V(K)]LN[V(K)]. Therefore LN[V(H)V(K)]LN[V(H)]LN[V(K)]. Let vLN[V(H)]LN[V(K)]vLN[V(H)]andvLN[V(K)]. Hence by definition N(v)V(H) and N(v)V(K)N(v)V(H)V(K). This means that vLN[V(H)V(K)]. Therefore LN[V(H)]LN[V(K)]LN[V(H)V(K)]. Hence, we conclude that LN[V(H)]LN[V(K)]=LN[V(H)V(K)].

(d)

Since V(H)V(H)V(K),V(K)V(H)V(K),UN[V(H)]UN[V(H)V(K)] and UN[V(K)]UN[V(H)V(K)]. Therefore UN[V(H)]UN[V(K)]UN[V(H)V(K)]. Let vUN[V(H)V(K)], then by definition x{N(v):v[V(H)V(K)]}x{N(v):vV(H)}orx{N(v):vV(K)xUN[V(H)]orxUN[V(K)]xUN[V(H)]UN[V(K)]. Therefore UN[V(H)V(K)]UN[V(H)]UN[V(K)]. Hence, we conclude that UN[V(H)V(K)]=UN[V(H)]UN[V(K)].

(e)

Since V(H)V(K)V(H),V(H)V(K)V(K),UN[V(H)V(K)]UN[V(H)] and UN[V(H)V(K)]UN[V(K)]. Therefore UN[V(H)V(K)]UN[V(H)]UN[V(K)].

Example 3.7

Consider Figure

Then V(G)={a,b,c,d,e} and N(a)={a,c},N(b)={a,b,c},N(c)={c,e},N(d)={a,d,e}. Table shows the nanotopology of any subgraph H of a subgraph of G.

Figure 2. Graph for Example 3.7 and Remark 3.8.

Figure 2. Graph for Example 3.7 and Remark 3.8.

Table 1. Nanotopology for the possible subgraphs of G

Remark 3.8

Let G[V, E] be a graph, H and K are two subgraphs of G. Then from the examples 3.7 we can see some perception as follows:

(i)

L[V(H)V(K)]L[V(H)]L[V(K)], take V(H)={a,b}andV(K)={c}

(ii)

U[V(H)]U[V(K)]U[V(H)V(K)], take V(H)={a,d}andV(K)={a,e}

(iii)

L[V(H)]c[U[V(H)]]c, take V(H)={a}

(iv)

U[V(H)]c[L[V(H)]]c, take V(H)={a,b}

(v)

U[U[V(H)]][U[V(H)]], take V(H)={a}

(vi)

U[V(H)]L[U[V(H)]], take V(H)={a,c}

(vii)

L[U[V(H)]]V(H), take V(H)={b}

(viii)

V(H)U[L[V(H)]], take V(H)={a}

(ix)

U[L[V(H)]]L[V(H)], take V(H)={a,c}

(x)

L[V(H)]L[L[V(H)]], take V(H)={a,c}.

Theorem 3.9

Let G[V,E], H is a subgraph of G, then U[L[V(H)]]V(H)L[U[V(H)]].

Proof

Let xU[L[V(H)]] there exists a vL[V(H)] such that vxE[G], therefore xN(v)V(H).

Now, since xV(H), then N(x)U[V(H)] implies, xL[U[V(H)]].

Theorem 3.10

Let G[V,E], H is a subgraph of G, then

(i)

L[U[L[V(H)]]]=L[V(H)].

(ii)

U[L[U[V(H)]]]=U[V(H)].

Proof

 

(i)

Let xL[V(H)]N(x)U[L[V(H)]]. So xL[U[L[V(H)]]] we know that U[L[V(H)]]V(H), implies L[U[L[V(H)]]]=L[V(H)].

(ii)

we know that U[L[V(H)]]V(H) implies U[L[U[V(H)]]]U[V(H)] we know that V(H)L[U[[V(H)]] implies U[L[U[V(H)]]]=U[V(H)].

4. Formalizing structural equivalence

Here we are formalizing the structural equivalence for the graphs and their corresponding nanotopologies generated by them.

Remark 4.1

In this section we define graphical isomorphism is a related task for deciding when two graphs with different specifications are structurally equivalent, that is whether they have the same pattern of connections. Nanohomeomorphism between two nanotopological spaces are said to be topologically equivalent. Here we are formalizing the structural equivalence for the graphs and their corresponding nanotopologies generated by them.

Definition 4.2

(Hsu & Lin, Citation2008) Two digraphs G and H are isomorphic if there is an isomorphism f between their underlying graphs that preserves the direction of each edge. That is, e is directed from u to v if and only if f(e) is directed from f(u) to f(v).

Definition 4.3

(Hsu & Lin, Citation2008) Two digraphs Cand D are isomorphic if D can be obtained by relabelling the vertices of C, that is, if there is a bijection between the vertices of C and those of D, such that the arcs joining each pair of vertices in C agree in both number and direction with the arcs joining the corresponding pair of vertices in D.

Definition 4.4

Let (U,τR(X)) and (V,τR(Y)) be nanotopological spaces, then the mapping f:(U,τR(X))(V,τR(Y)) is said to be a nanocontinuous on U if the inverse image of every nano-open set in V is nano-open in U.

Definition 4.5

Let (U,τR(X)) and (V,τR(Y)) be a nanotopological spaces, then the mapping f:(U,τR(X))(V,τR(Y)) is said to be a nanohomeomorphism if

(i)

f is 1–1 and onto

(ii)

f is nanocontinuous

(iii)

f is nano-open

Example 4.6

Let G = [V,E] and G’= [V’,E’] be two isomorphic graphs, where V= {v1,v2,v3,v4}, E = {(v1,v2),(v1,v4),(v2,v4),(v4,v3),(v3,v2)}, V’ = {u1,u2,u3,u4} and E’ = {(u1,u3),(u2,u1),(u3,u2),(u4,u1),(u4,u3)}.

Then there exists a function f:VV such that f(v1)=u4,f(v2)=u1,f(v3)=u2,f(v4)=u3. Let H be any subgraph of G and V(H) = {v2,v3}. Then the nanotopology generated by vertices of V(H) and V(f(H)) are τN[V(H)]={V(G),,{v3},{v2,v3,v4},{v2,v4}} and τN[f(V(H))]={V(G),,{u2},{u1,u2,u3},{u1,u3}}. Then the function ϕ:[V(G),τN(V(H))][V(G),τN(f(V(H))] is a homeomorphism (Figure ).

Figure 3. Isomorphic graphs.

Figure 3. Isomorphic graphs.

Theorem 4.7

Let G = [V,E] and G’ = [V’,E’] be any two isomorphic graphs then there exists a homeomorphism ϕ:[V(G),τN(V(H))][V(G),τN(f(V(H))] for every subgraph H of G.

Proof

Since G and G’ are isomorphic by defn. there is an isomorphism f:V[G]V[G] between their uderlying graphs that preserves the direction of each edge and also N(x) = N(f(x)) xV(G). Suppose [V(G),τN(V(H))] and [V(G),τN(f(V(H))] be the nanotopological space generated by V(H) and f(V(H)). Since f is a bijection clearly, it follows that ϕ is 1–1 and onto.

(i)

To prove that ϕ is an open map. Let A be any nano-open set in τN(V(H)), then ϕ(A) is nano-open since N(x) = N(f(x)) xA.

(ii)

To prove that ϕ is continuous. Let B be any nano-open set in τN(f(V(H)), then ϕ-1[B] is nano-open in τN[V(H)].

Thus ϕ is a homeomorphism.

5. Computer chip intellectual property rights

Based on the structural equivalence of graphs and the corresponding nanotopology induced by them, we have made an attempt to check whether the chip produced by a company have striking operational similarity produced by the another company.

Suppose that not long after Corporation X develops and markets a computer chip, it happens that the Corporation Y markets a chip with striking operational similarities. If Corporation X could prove that Corporation Y’s circuit is merely a rearrangement of the CorporationX circuitry that is the circuitries are isomorphic], they might have the basis for a patent infringement suit.

Algorithm to detect patent infringement suit: Step1: Given the electrical circuit of the chips manufactured by two companies. An electrical network is an interconnection of electrical network elements such as resistances, capacitances, inductances, voltage and current sources, etc., We also assign reference direction by a directed edge results in the directed graph representing the network.

Step2: Convert the electrical circuits C1 and C2 into graphs G1 and G2.

Step3: Check whether G1 and G2 are isomorphic, and their corresponding nanotopologies induced from their vertices are homeomorphic.

Step4: If G1G2 and [V(G),τN(V(H))][V(G),τN(f(V(H))] then the corresponding circuitries have striking operational similarities, and the company X can claim on the basis for a patent infringement suit.

Step5: Otherwise, we can conclude that both the chip produced are entirely different.

Step1: Consider the following basic circuit of the chip manufactured by two companies Corporation X and Corporation Y. Using the above algorithm we can prove whether these two circuits have functional similarities via nanotopology induced by the vertices of its subgraphs (Figure ).

Figure 4. Electrical circuit of chips produced by X and Y.

Figure 4. Electrical circuit of chips produced by X and Y.

Step2: The graphs are good pictorial representations of circuits and capture all their structural characteristics. Transform the basic circuit C1 and C2 of the chip produced by Corporation X and Corporation Y into graphs G1=[V1,E1] and G2=[V2,E2], respectively (Figure ).

Figure 5. Graphs for circuit C1 and circuit C2.

Figure 5. Graphs for circuit C1 and circuit C2.

Step3: From the following graph we define a function f:V1V2 such that f(1) = b, f(2) = a, f(3) = c, f(4) = d and clearly f is an isomorphism. Since G2 can be obtained by relabelling the vertices of G1, that is, f is a bijection between the vertices of G1 and those of G2, such that the arcs joining each pair of vertices in G1 agree in both number and direction with the arcs joining the corresponding pair of vertices in G2.

Then we also have to check ϕ:[V(G),τN(V(H))][V(G),τN(f(V(H))] is a homeomorphism for every subgraph H of G.

Since f is a bijection clearly, it follows that ϕ is 1–1 and onto.

(i)

To prove that ϕ is an open map.

Then the nanotopology generated by vertices of V(H) = {1,3} and V(f(H))={b,c} are τN[V(H)]={V(G1),,{3},{1,2,3},{1,2}} and τN[f(V(H))]={V(G2),,{c},{a,b,c},{a,b}}.

Then the function ϕ:[V(G1),τN(V(H))][V(G2),τN(f(V(H))] is a homeomorphism. This holds for every subgraph H of G1 (Table ).

Table 2. Nanotopolgy for V(H) and f(V(H))

Step4: From the above process, we can conclude that the graph of the circuits and their corresponding nanotopologies generated by the vertices of the subgraphs are homeomorphic.

Step5: Thus we can characterize that the chips manufactured by Corporation Y is just a rearrangement of CorporationX and also they have striking operational similarities and CorporationX can also claim for his patent infringement suit.

Observation: Using the above structural equivalence technique we can check whether two circuits are equivalent and we can also extend our theory in many industrial products for patent infringement suit.

6. Conclusion

The purpose of the present work was to put a starting point for the application of nanotopology via graph theory. We believe that nanotopological graph structure will be an important base for modification of knowledge extraction and processing.

Additional information

Funding

Funding. The authors received no direct funding for this research.

Notes on contributors

M. Lellis Thivagar

M. Lellis Thivagar has published 210 research publications both in National and International journals to his credit. In his collaborative work, he has joined hands with intellectuals of high reputed persons internationally. He serves as a referee for 12 peer-reviewed international journals. At present he is the professor & chair person, School Of Mathematics, Madurai Kamaraj University.

Paul Manuel

Paul Manuel has published 114 research publications both in National and International journals to his credit. He is expertise in Graph Algorithms, Combinatorial chemistry and Grid computing and also reviewer of many prestigious professional bodies. Currently he is an Professor, Department of Information sciences, Kuwait University, Kuwait.

V. Sutha Devi

V. Sutha Devi is a research scholar of Mathematics under the guidance of M. Lellis Thivagar at the School of Mathematics, Madurai Kamaraj University, Madurai. She had 9 years of working experience as Assistant Professor of Mathematics. She has attended and presented two papers in international conferences. Four of her research papers are published/accepted in the reputed international peer-reviewed journals.

References

  • Bonikowski, Z., Bryniarski, E., & Wybraniec, U. (1998). Extensions and intentions in the rough set theory. Information Sciences, 107, 149–167.
  • Deseor, C. A., & Kuh, E. S. (2009). Basic circuit theory. Berkeley, CA: Tata McGraw-Hill.
  • Diestel, R. (2010). Graph theory II. Heidelberg: Springer-Verlag IV.
  • Jensen, R., & Shen, Q. (2007). Fuzzy-rough sets assisted attribute selection. IEEE Transactions on Fuzzy System, 15, 73–89.
  • Lellis Thivagar, M., & Richard, C. (2013a). On nano forms of weakly open sets. International Journal of Mathematics and Statistics, 1, 31–37. Retrieved from www.ijmsi.org [version 0.11e0111031037].
  • Lellis Thivagar, M., & Richard, C. (2013b). On nano continuity. Journal of Mathematical Theory and Modelling, 3, 32–37.
  • Hsu, L. H., & Lin, C. K. (2008). Graph theory and interconnection networks. CRC Press.