Fast deblocking filter with highly parallel and pipelined architecture for H.264/AVC decoder

Abstract

The deblocking filter (DBF) is a system bottleneck of the whole decoder in terms of processing cycles. Based on the study and analysis of the basic filtering order and previously presented filtering orders, we put forward a competitive filtering scheme to reduce the filtering cycles and improve the system throughput. Then, a highly parallel and pipelined deblocking filter architecture is proposed accordingly. Comparison of various DBF solutions shows that the system performance of our proposal significantly outperforms the previous designs from 3·7 to 8·3 times. Moreover, our architecture can easily support real-time deblocking of 60 fps HDTV video, and it can be suitably integrated into the H.264/AVC decoder.

Keywords:

• deblocking filter
• H.264/AVC
• filtering order
• throughput
• VLSI

This work was supported by the National Youth Science Foundation of China under grant no. 11004048. In addition, the authors would like to thank Haitao Chen for providing helpful suggestions to improve this manuscript.