Design and Implementation of Online Clock Skew Scheme-based Asynchronous Wave-pipelined Distributed Arithmetic Filters on FPGA

Abstract

In this paper, Design and implementation of asynchronous wave-pipelined (WP) Distributed Arithmetic (DA) Alters on FPGA using online clock skew scheme is proposed. DA Alters of 8-taps, 16-taps, and 32-taps are implemented on an FPGA using non-pipelining (NP), pipelining, and WP schemes and compared with that of self-tuned scheme reported in the literature. The WP DA filters operate 1.4 to 1.53 times faster than NP DA filters. The delay-power products of the WP DA filters of 8-taps, 16-taps, and 32-taps using Online Clock Skew Scheme are less by 51.24%, 29.6%, and 3.78%, respectively, compared to those using Self-tuned Scheme.

Keywords:

• Delav-aower aroduct
• Distributed arithmetic
• Filter
• FPGA
• Wave-aiaelinina
• Online clock skew scheme

Additional information

Notes on contributors

M. Santhi

M. Santhi received her B.E. (ECE) Degree from Bharathidasan University, Tiruchirappalli, Tamilnadu, India in 1990. She received her M.E.(VLSI Systems) Degree from Regional Engineering College, Tiruchirappalli, Tamilnadu, India in 2003. She has submitted thesis as a part of her Ph.D. Degree in National Institute of Technology (NIT), Tiruchirappalli, Tamilnadu, India. She is currently working as Head of the Department in the Department of ECE of Saranathan College of Engineering, Tiruchirappalli, Tamilnadu, India. She has 17 years teaching experience. She has 14 International/National Journals and Conferences. Her Research areas include VLSI Signal Processing, Asynchronous Techniques, Wave-Pipelining Techniques, Wireless Standard PHY Layer. E-mail: [email protected]

G. Lakshminarayanan

G. Lakshminarayanan received his M.E. and Ph.D. degrees in ECE from Bharathidasan University, Tiruchirappalli, India, in 1995 and 2005, respectively. He previously worked as Service Engineer for approximately five years and as a Scientist and Research Associate for approximately four years in Regional Engineering College, Tiruchirappalli, India. He worked as a Senior Design Engineer with Sasken Communication Technologies, Limited, Bangalore, India from November 2004 to August 2005. He was a Faculty Member in Sastra, Tanjore, India, for one semester. He is currently working as an Associate Professor in the Department of Electronics and Communication Engineering, National Institute of Technology, Tiruchirappalli (Formally known as Regional Engineering College, Tiruchirappalli). He has published numerous papers in international journals and conferences. His current research interests include FPGA based System design, VLSI Signal Processing, Reconfigurable Systems, Asynchronous Systems, VLSI based Wireless System Design, Algorithms and Techniques for Cognitive Radio and Network on Chip. E-mail: [email protected]

B. Venkataramani

B. Venkataramani received the B.E. degree in Electronics and communication engineering from Regional Engineering College, Tiruchirappalli, India, in 1979 and the M.Tech. and Ph.D. degrees in electrical engineering from Indian Institute of Technology, Kanpur, India, in 1984 and 1996, respectively. He worked as Deputy Engineer in Bharath Electronics, Ltd., Bangalore, India, and as a Research Engineer in the Indian Institute of Technology, each for approximately three years. Since 1987, he has been with the faculty of the National Institute of Technology, Trichy (Formerly known as Regional Engineering College, Trichy). Currently he is the Professor of the Electronics and Communication Department. He has published two books and numerous papers in journals and international conferences. His current research interests include field-programmable gate array (FPGA) and system on a single chip (SOC)-based system design and performance analysis of high-speed computer networks, Analog VLSI, Image and Speech Processing. E-mail: [email protected]