Design and FPGA Implementation of a Pseudo Random Bit Generator Using Chaotic Maps

Abstract

In this paper, a random bit sequence generator based on chaotic maps is introduced and implemented. In this generator, two chaotic map functions with two different keys are used. The Bifurcation diagram is used to calculate the initial state of the chaotic maps in order to produce the output random bit sequence. Chaotic Logistic and Tent maps classically are defined in an analogue space. In order to implement these chaotic maps on a hardware digital platform, these chaotic maps are modified. Digital chaotic Logistic and Tent maps are introduced. A design for implementation of these modified chaotic maps is also presented. The output bits of two chaotic maps are EX-ORed to produce a random sequence of 1 000 000 bits. These designs are implemented on Field Programmable Gate Array, and the results are reported. The proposed designs are tested by producing 100 samples of 1 000 000 bits, and they pass the standard Federal Information Processing Standard 140-1 and National Institute of Standards and Technology statistical tests for random bit generators.

Keywords:

• Bifurcation
• Chaotic map
• Digital implementation
• Random bit sequence

Additional information

Notes on contributors

Himan Khanzadi

Himan Khanzadi (BS.2005, M.S.2010), Himan Khanzadi is born in Kurdistan of Iran in 1982 and got his BS.degree in Electrical Engineering from Kerman university of Iran in 2005. He got his MS degree in EE in Shahid Behesti University, Tehran, Iran in 2010. His research interests are Chaotic Cryptosystems, Random Number Generator, Digital Circuit Design and FPGA. E-mail: [email protected]

Mohammad Eshghi

Mohammad Eshghi (BS’78, Ms’89, and Phd’94) Mohammad Eshghi is born in Shahroud, Iran in 1954 and got his BS in Electrical Engineering from Sharif University in 1978. He got his MS degree in EE from Ohio University, Athens, Ohio, and his PhD in EE from Ohio State University, Columbus, Ohio, USA, in 1989 and 1994, respectively.

He is now with the Electrical and Computer engineering Faculty at Shahid Beheshti University, Tehran Iran. His research interest including Digital Signal processing, Digital circuit design and implementation on Field Programmable Gate Array (FPGA), Chaotic systems, and Quantum computing. E-mail: [email protected].

Shahram Etemadi Borujeni

Shahram Etemadi Borujeni, (BSc’87, MTech’92, PhD 2010) Shahram Etemadi Borujeni is born in Borujen, Iran in 1964. He got his B.Sc. in Electrical Engineering from Iranian University of Science and Technology in 1987, and his MTech degree in Radar and Communication Engineering from Indian Institute of Technology, Delhi in 1992. He is with Computer Engineering Department at Isfahan University, Isfahan Iran since 1992. Meanwhile, He got his PhD degree in Computer Architecture Engineering at Shahid Beheshti University, Iran, in 2010. His research interest includes Multimedia and Chaotic Cryptography, Automation & Robotics, and Industrial application of Computer. E-mail: [email protected]