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Abstract
This paper presents a high-conversion gain, low-power, folded CMOS mixer for ZigBee application in 2.4 GHz of user bandwidth. The proposed mixer adapts current reuse technique to increase the conversion gain while substantially reducing the DC power dissipation. The current from LO stage is reused at the transconductance stage to reduce the power consumption. This mixer is verified in 0.13 μm standard CMOS technology. The simulation result exhibits a high-conversion gain performance (CG) of 10 dB, 1 dB compression point (P1 dB) of -13.43 dBm, third-order intercept point (IIP3) of -4.3 dBm, and a noise figure of 16.67 dB. The circuit draws 675 μA current from the 1.2 V of supply voltage headroom.
Additional information
Notes on contributors
G. H. Tan
G. H. Tan received the B.S. and M.S degrees in electronic engineering from University Putra Malaysia in 1999 and 2001, respectively. Currently, he is working toward the PhD degree in University Putra Malaysia, Malaysia. His current research interest includes analogue and Radio Frequency Integrated Circuit Design. E-mail: [email protected]
M. S. Roslina
M. S. Roslina received her B.Sc. (Electrical Engineering) degree from George Washington University, Washington D.C, USA, in 1990. She received M.Sc (Microelectronics Systems Design) degree in 1992 and Ph.D degree in 1999 from University of Southampton, UK. She is currently a lecturer in the department of Electrical and Electronic Engineering, University Putra Malaysia. Her research interests include semiconductor devices and IC design. E-mail: [email protected]
H. Ramiah
H. Ramiah received the B.E., M.S., and Ph.D. degrees in electrical and electronics engineering, majoring in analog and digital IC design from University Science Malaysia, Penang, Malaysia, in 2000, 2003, and 2009, respectively. In the year 2003, he was with Sires Labs Sdn. Bhd, Cyberjaya, Malaysia, working on audio pre-amplifier for MEMs ASIC application and the design of 10Gbps optical transceiver solution. In year 2002, he was with Intel Technology Sdn. Bhd., Penang, Malaysia, performing high-frequency signal integrity analysis for high-speed digital data transmission and developing Matlab spread sheet for Eye diagram generation, to evaluate signal response for FCBGA and FCMMAP packages. Currently, he is a Senior Lecturer in the Department of Electrical Engineering, University Malaya. Dr. Harikrishnan was the recipient of Intel Fellowship Grant Award, from 2000 to 2006. His research work has resulted in several technical publications. His main research interest includes Analog Integrated Circuit Design, RFIC Design, and VLSI system design. E-mail: [email protected]
W. K. Chong
W. K. Chong received the B.S. degree in electronic engineering from University Malaysia Perlis, Malaysia, in 2008. Currently, he is working toward the M.S degree in the University of Malaya, Kuala Lumpur, Malaysia. His current research interest includes analogue and Radio Frequency Integrated Circuit Design. E-mail: [email protected]