Reliable Implementation on SRAM-based FPGA using Evolutionary Methods

Abstract

The mitigation of Single Event Upset (SEU), in the implemented circuits on SRAM-based FPGAs is a crucial issue with increasing usage of such chips in aerospace applications. In this paper, three evolutionary methods have been developed to reduce Soft Error Rate (SER) of such circuits. The first two methods are based on Genetic Algorithm (GA) and Particle Swarm Optimization (PSO), and the other one is a co-evolutionary method which improves the convergence rate and cost of the former methods. The efficiency of these methods has been shown by comparing SER of implemented circuits using these methods with Versatile Place and Route (VPR) counterparts. More than 35% in SER reduction has been achieved for some MCNC benchmark circuits.

Keywords:

• Genetic algorithm
• Place and route
• Particle swarm optimization
• Soft error rate
• SRAM-based field programmable gate arrays

Additional information

Notes on contributors

Hadi Jahanirad

Hadi Jahanirad is a PhD student in Electronics Engineering at Iran University of Science and Technology, Tehran, Iran. His research interests are in the area of VLSI and fault tolerant circuits design. E-mail: [email protected]

Karim Mohammadi

Karim Mohammadi is a professor in the department of Electrical Engineering at Iran University of Science and Technology, Tehran, Iran. His research interests are in the area of fault tolerant and digital circuits design. E-mail: [email protected]