Multiple Parallel Concatenated Gallager Codes: Code Design and Decoding Techniques

Abstract

A novel technique to concatenate multiple component low density parity check (LDPC) codes in parallel is presented. Multiple Parallel Concatenated Gallager Codes leverage the advantage of breaking an equivalently long LDPC code into multiple small (lower-complexity) LDPC codes to offer scalability and scope for improving performance in practical implementation for delay-sensitive and resource-constrained applications. The construction as well as two proposed decoding techniques for MPCGCs is evaluated. It is shown that by optimizing the construction of the component LDPC codes and the number of decoding iterations at various channel conditions, the performance of MPCGCs can be significantly improved and their complexity reduced.

Keywords:

• Iterative decoding
• Low density parity check
• Parallel concatenation
• Parallel concatenated gallager codes
• Turbo codes

Additional information

Notes on contributors

Hatim M. Behairy

Hatim M. Behairy received the M.Sc. in Electrical Engineering and Ph.D. in Information Technology degrees from George Mason University, Virginia, USA, in 1997 and 2002, respectively. He has been with the National Electronics, Communication and Photonics Center at King Abdulaziz City for Science and Technology, Riyadh, Saudi Arabia since 2003. His research interests are in the design of new error correction coding techniques for next-generation broadband wireless communication systems, using turbo-coding principles. E-mail: [email protected]

Mohammed Benaissa

Mohammed Benaissa received the Ph.D. degree in VLSI signal processing from the University of Newcastle, Upon Tyne, UK, in 1990. He has been with the Department of Electronic and Electrical Engineering, University of Sheffield, Sheffield, UK, since 1999. His research interests include hardware cryptography, error control coding hardware implementation, reconfigurable hardware design, Galois field arithmetic, and residue number systems. He has published more than 100 papers on contributions to algorithmic, architectural, and circuit issues in these areas. He is a Senior Member of the IEEE and has served on the Technical Program Committees of numerous conferences. E-mail: [email protected]