FPGA-based Low Power Audio Subword Sorter Unit

Abstract

The security of audio data in high end communication applications like satellites and radars is an issue of concern these days. Designing a processor at the chip level for this requirement is by itself a challenge to VLSI engineers. This paper aims to design a HDL based novel audio subword sorter unit, which is less complex in structure and highly efficient in terms of security. In this paper, we examine the hardware implementation of powerful permutation instruction group (GRP) with low power. This is done at the integrated chip (IC-level) using Verilog HDL and can be implemented in FPGA. To our knowledge this is the first audio subword sorter unit implemented in FPGA.

Keywords:

• Audio subword sorter
• Cryptography
• Permutation
• Multimedia network security

Additional information

Notes on contributors

P. Karthigaikumar

P. Karthigaikumar received his Bachelor of Engineering degree in Electrical and Electronics Engineering from the Bharathiar University, India in 1999 and his Master of Engineering degree with Distinction in Applied Electronics from Bharathiar University, India in 2003. He is pursuing Ph. D degree in Anna University-Coimbatore, India from 2007, focusing on Media Security processor. He is the member of International Association of Engineers (MIAENG) and member of International Association of Computer sciences and Information Technology (MIACSIT). He joined Karunya University, Coimbatore, India in 2000.He is now Assistant Professor in Electronics and Communication Engineering. His research interest includes FPGA implementation of Crypto algorithm, FPGA implementation of Watermarking algorithm and reconfigurable processor. E-mail: [email protected]

K Baskaran

K. Baskaran received his Bachelor of Engineering degree in Electrical and Electronics Engineering from the Annamalai University, India in 1989, Master of Engineering degree in Computer Science Engineering from Bharathiar University, India in 2002 and Ph. D degree from Anna University-Chennai, India in 2006. He is a member of IEEE and member of ISTE. He is now Assistant Professor in Computer Science and Engineering, Government college of Technology, Coimbatore, India . His area of interest includes Adhoc networks, network security etc., E-mail: [email protected]