Design of SIPC based LC-QVCO in 0.18 ¼m CMOS Technology and the Impact of Coupling Factor, K

Abstract

This paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage-controlled oscillator (QVCO), realized with pMOS transistors, relaxing the sensitivity to substrate-induced noise and flicker noise, 1/f effect. A stacked planar spiral inductor exhibiting a Q factor of 5.8, with a pMOS-based varactor of 32% tuning range is implemented in 0.18 ¼m CMOS technology. The phase noise of the SIPC QVCO architecture simulated at 1 MHz of offset frequency is observed to be -111.43 dBc/Hz, in comparison with the phase noise of a conventional QVCO architecture which is observed to be -106.15 dBc/Hz, while dissipating the same amount of power about 14.6 mW. The effect of coupling factor, K to the amplitude and phase noise degradation is also investigated and verified.

Keywords:

• Phase noise
• pMOS varactor
• Quadrature voltage-controlled oscillator
• Source injection parallel coupled quadrature VCO
• Stacked spiral inductor

Additional information

Notes on contributors

Harikrishnan Ramiah

Harikrishnan Ramiah is currently a Senior Lecturer at Department of Electrical Engineering, University of Malaya, working in the area of RFIC design and Electromagnetic Modeling. He received his B. Eng(Hons), MSc and PhD degrees in Electrical and Electronic Engineering, in the field of Analog and Digital IC design from Universiti Sains Malaysia in 2000, 2003 and 2008 respectively. He was with Intel Technology, Sdn. Bhd attached in the power gating development of 45 nm process at the MCDC, I/O design group, Penang. In the year 2003, he was with SiresLabs Sdn. Bhd, CyberJaya, Malaysia. At the year 2002, he was attached to Intel Technology, Sdn.Bhd performing high frequency signal integrity analysis for high speed digital data transmission and developing Matlab spread sheet for Eye diagram generation, to evaluate signal response for FCBGA and FCMMAP packages. He was the recipient of Intel Fellowship Grant Award, 2000-2008. He received the Best Paper Awards from ICAST (International Conference on Advances in Strategic Technologies), 2003 Conference. His research work has resulted in 23 technical publications. His main research interest includes Analog Integrated Circuit Design, RFIC Design, VLSI system design and Electromagnetic Modeling. E-mail : [email protected]

Jeevan Kanesan

Jeevan Kanesan obtained PhD and MSc from Univesity Science Malaysia in 2003 and 2007 respectively. He worked as Thermal Engineer at Intel, Penang. He is currently based in University Malaya. He has published more than 20 international journal and conference papers. His research interest includes design automation tool(CAD), artificial intelligence, computational electromagnectics and thermal analysis in IC design. E-mail : [email protected]

Tun Zainal Azni Zulkifli

Tun Zainal Azni Zulkifli received BSc, MSc and DSc in Electrical Engineering from Washington University in St. Louis in 1995, 1998 and 2002, respectively. Prior to 1995, he spent 2 years working as product engineer in NEC Sem. (M) Sdn Bhd where he was responsible for various products such as regulators, amplifiers, etc. He completed and co-lead MP-45g line transfer from NEC Fukui to Malaysia, in 2005. Since 2002, he is with Universiti Sains Malaysia leading RFIC Group developing various wireless tranceivers for UWB, RFID and WCDMA specifically. He is also interested in pursuing some data converters implementation and FFT development. He has over 40 technical publications and successfully supervised 3 MSc students to date. In 2005, he co-designed successfully active RFID RF Front End specifically LNA, Mixers and Bandgap Reference for Jaalaa Inc.Lake Forest, CA E-mail: [email protected]