Circuit Level Implementation for Insulated Shallow Extension Silicon on Nothing (ISE-SON) MOSFET: A Novel Device Architecture

Abstract

In this paper, circuit performance of Insulated Shallow Extension Silicon On Nothing (ISESON) architecture is investigated. A comparative analysis of ISESON, Silicon On Nothing (SON), and Insulated Shallow Extension (ISE) architecture has been carried out to explore the potential of the devices for low-voltage digital applications, i.e., in terms of combinational and static sequential circuits. The relatively enhanced device performance, lower parasitic capacitances, and improved reliability issues in terms of interface charges at the SiO₂/Si interface of ISE-SON over SON, and ISE MOSFET for 22 nm channel length proves the suitability of the architecture for low-voltage digital applications.

Keywords:

• Dielectric pocket
• Digital circuits
• N-MOS inverter
• Robustness against interface charges
• Silicon on nothing

Additional information

Notes on contributors

Vandana Kumari

Vandana Kumari was born in New Delhi, India, in 1986. She received the B.Sc. (Gen) and M.Sc. degrees in Electronics from the University of Delhi, Delhi, India in 2006 and 2009, respectively. She is currently pursuing the Ph.D. degree in Electronics at the Semiconductor Device Research Laboratory, Department of Electronics Science, University of Delhi, and South Campus.

Her current research interests are in the area of modeling and simulation of Insulated Shallow Extension, Silicon on Nothing and III-V compound semiconductor based MOSFETs. She has authored 15 papers in various international journals and conferences. E-mail: [email protected]

Manoj Saxena

Manoj Saxena was born in New Delhi, India, on August 14, 1977. He received the B.Sc. (with honors), M. Sc., and Ph.D. degrees from the University of Delhi, New Delhi, in 1998, 2000, and 2006, respectively, all in Electronics. He joined Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi in 2000 and presently he is Associate Professor. He has authored/coauthored more than 170 technical papers in international journals and conferences. His current research interests are in the areas of analytical modeling, design, and simulation of Optically controlled MESFET/ MOSFET, silicon-on-nothing, insulated-shallow-extension, cylindrical gate MOSFET and Tunnel FET. E-mail: [email protected]

Radhey Shayam Gupta

Radhey Shayam Gupta received the B.Sc. and M.Sc. degrees from Agra University, Agra, India, in 1963 and 1966, respectively, and the Ph.D. degree in electronic engineering from the Institute of Technology, Banaras Hindu University, Varanasi, India, in 1970. He has authored or coauthored more than 600 papers in various international and national journals and conference proceedings and supervised 46 Ph. D students. Currently he is Professor and Head in Department of ECE, Maharaja Agrasen Institute of Technology (GGIP University, Delhi). His current interests and activities include modeling and simulations of HEMTs, and advance MOSFET device designs. E-mail: [email protected]

Mridula Gupta

Mridula Gupta received the B.Sc. degree in physics, the M.Sc. degree in Electronics, the M.Tech. degree in Microwave Electronics, and the Ph.D. degree in Optoelectronics from the University of Delhi, Delhi, India, in 1984, 1986, 1988, and 1998, respectively. Since 1989, she has been with the Department of Electronic Science, University of Delhi South Campus, New Delhi, India, where she was previously a Lecturer and is currently an Professor and with the Semiconductor Devices Research Laboratory. She has authored or coauthored approximately 330 publications in international and national journals and conference proceedings. Her current research interests include modeling and simulation of MOSFETs, MESFETs, and HEMTs, for microwave applications. E-mail: [email protected]