A CMOS Up-conversion Mixer in 0.18 μm Technology for IEEE 802.11a WLAN Application

Abstract

This paper describes a 3.5-GHz up-conversion mixer core utilized in a two-step transmitter architecture in compliance with IEEE 802.11a WLAN application. The architecture is based on current-draining folded architecture and is implemented in 0.18-μm CMOS technology, which alleviates the need of bulky resonator integration. The main advantages of the introduced mixer topology are high linearity and high isolation. The low-voltage architecture consumes 5.17 mA of current from 1.8-V supply and shows −2.09-dBm IIP₃ and −9.82-dBm IP_1dB. The proposed architecture observes an output power of −43.69 dBm at the up-converted 3.7 GHz sideband, with −30 dBm and −10 dBm of input baseband and local oscillator power, respectively.

Keywords:

• CMOS mixers
• Current-draining folded architecture
• Low voltage switched transconductor topology

Additional information

Notes on contributors

Harikrishnan Ramiah

Harikrishnan Ramiah is currently a Senior Lecturer at Department of Electrical Engineering, University of Malaya, Malaysia, working in the area of RFIC design and Electromagnetic Modeling. He received his B. Eng(Hons), MSc and PhD degrees in Electrical and Electronic Engineering, in the field of Analog and Digital IC design from University Science Malaysia, Malaysia in 2000, 2003 and 2008 respectively. He was the recipient of Intel Fellowship Grant Award, 2000–2008. He received the Best Paper Awards from ICAST (International Conference on Advances in Strategic Technologies), 2003 Conference. His research work has resulted into various technical publications. His main research interest includes Analog Integrated Circuit Design, RFIC Design, VLSI system design and Electromagnetic Modeling. Dr. Harikrishnan is a Chartered Engineer member of Institute of Electrical Technology (IET), member of IEEE and IEICE. E-mail: [email protected]

Jeevan Kanesan

Jeevan Kanesan received his B.S. degree in electrical & electronics engineering from University Technology Malaysia, Malaysia, in 1999, M.S. degree and Ph.D. degree in mechanical engineering from University Science Malaysia, Malaysia in 2003 and 2006 respectively. From 2000 to 2001, he has worked as equipment engineer at Carsem Semiconductor, Malaysia and IC Design engineer in the thermo-mechanical department, Intel Technology Sdn. Bhd., Malaysia from 2006 to 2008. He has been with University of Malaya, Malaysia as a Senior Lecturer in the electrical engineering department since 2008. His research interests include CAD of VLSI circuits and design and analysis of algorithms. E-mail: [email protected]

Tun Zainal Azni Zulkifli

Tun Zainal Azni Zulkifli received BSc, MSc and DSc in Electrical Engineering from Washington University in St. Louis in 1995, 1998 and 2002, respectively. Prior to 1995, he spent 2 years working as product engineer in NEC Sem. (M) Sdn Bhd where he was responsible for various products such as regulators, amplifiers, etc. He completed and co-lead MP-45g line transfer from NEC Fukui to Malaysia, in 2005. Since 2002, he is with Universiti Sains Malaysia leading RFIC Group developing various wireless tranceivers for UWB, RFID and WCDMA specifically. He is also interested in pursuing some data converters implementation and FFT development. He has over 40 technical publications and successfully supervised 3 MSc students to date. In 2005, he co-designed successfully active RFID RF Front End specifically LNA, Mixers and Bandgap Reference for Jaalaa Inc.Lake Forest, CA. E-mail: [email protected]