Gate Current Modelling through High-K Gate Stack MOSFET for Very-Large-Scale Integration Logic Circuit Analysis

Abstract

In this paper, we present a computationally efficient model for gate tunnelling current through different high-k gate dielectrics stack structures by adjusting two fitting parameters. The proposed model can be used in circuit simulator due to its simplicity in implementation. Various materials of high-k gate dielectrics stack have been examined and compared to analyse the reduction of gate leakage current by considering the effects of interfacial oxide thickness, type of gate stack, on current, off current, drain induced barrier lowering and sub-threshold slope. Consequently an optimised high-k gate dielectrics stack structure is proposed and used to analyse the gate leakage current in CMOS (complementary metal oxide semiconductor) based universal logic gates. The results obtained have been verified with Sentaurus simulation for the purpose of validation.

Keywords:

• MOSFET
• inelastic trap assisted tunneling
• gate tunnelling current
• high-k stack
• DIBL
• SS

Additional information

Notes on contributors

A.K. Rana

Ashwani K. Rana received his BTech degree in Electronics and Communication Engineering from National Institute of Technology, Hamirpur, India, in 1998 and MTech degree in very-large-scale integration (VLSI) technology from Indian Institute of Technology, Roorkee, India, in 2006. He is currently pursuing his PhD degree in nano-devices with the National Institute of Technology, Hamirpur, India. Presently he is with Department of Electronics and Communication Engineering, National Institute of Technology, Hamirpur, India, as an Assistant Professor. His research interests include modelling of semiconductor devices, low power high performance VLSI circuit design and emerging integrated circuit technologies.

N. Chand

Dr Narottam Chand received his PhD degree from IIT Roorkee in Computer Science and Engineering, India. Previously he received his MTech and BTech degrees in Computer Science and Engineering from IIT Delhi and NIT Hamirpur, India, respectively. Presently he is working as the Head of the Department of Computer Science and Engineering, NIT Hamirpur, India. His current research areas of interest include mobile computing, mobile ad-hoc networks and wireless sensor networks.

V. Kapoor

Dr Vinod Kapoor received his BE degree in Electronics & Communication Engineering from National Institute of Technology (formerly Regional Engineering College), Durgapur, West Bengal, India, in 1987 and Masters degree in Electronics & Control from Birla Institute of Technology & Science, Pilani (Rajasthan), India, in 1996. He received his PhD from Kurukshetra University, Kurukshetra, India, in the field of optical fibre communication in 2006. He also obtained his MBA degree with specialisation in Human Resources Management in 2002. He is presently Professor in the Department of Electronics & Communication Engineering NIT Hamirpur, India. His research interest includes optical fibre communication and optoelectronics/nano-devices. He has published more than 15 research papers in international/national journals and conferences, and guided four PhDs in these areas. He is member of ISTE, IETE and IE.