Area and Power Efficient Frequency Divider for Zigbee Frequency Synthesiser

Abstract

This paper proposes an area and power efficient frequency divider used in frequency synthesisers, which operates in 2.4 GHz IEEE 802.15.4/ZigBee frequency band. The proposed frequency divider consists of a multi-modulus pre-scaler and integrated P&S counter. In order to reduce the power consumption and area, swallow counter has been replaced by a simple digital circuit. Simulation results show 30% of area and power is reduced when compared to the previous design. All of the circuits can be designed in 0.18 µm complementary metal oxide semiconductor technology with a single 1.8 V DC voltage supply.

Keywords:

• DFF
• frequency synthesizer
• U-TSPC
• PLL
• true single-phase clock (TSPC)