A novel accelerator for dual-precision floating-point multiplication

ABSTRACT

This paper presents the new designs to speed up the floating-point multiplier by dividing the main multiplier into many sub-multipliers and allowing them to run concurrently. Also, this dividing enables the organisation of sub-multipliers that can process the data in single-precision format/double-precision format or others. In addition, the proposed design applies the pipeline model to build a new multiplier that can operate four multiplications at the same time. As a result, the proposed multiplier would process double-precision (64 bits) IEEE 754 format by dividing into four sub-multipliers (26 bits × 26 bits), and it achieves 26% to 47% faster than the conventional multiplier on different field programmable gate array platforms. The combinational multiplexers control the data path, which makes the multiplier able to process the single-precision number (32 bits) and the double-precision number (64 bits). Furthermore, the final result could be achieved after four stages instead of over four stages as in the state-of-the-art works.

KEYWORDS:

• Floating-point multiplier
• FPGA
• VLSI
• FPU
• embedded system