Citations (21)
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Seung-Kil Lim, Jae-Gon Kim & Hwa-Joong Kim. (2014) Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities. International Journal of Production Research 52:12, pages 3710-3724.
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J-G Kim & S-K Lim. (2012) Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process. Journal of the Operational Research Society 63:9, pages 1258-1270.
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Yang Sun, John W. Fowler & Dan L. Shunk. (2011) Policies for allocating product lots to customer orders in semiconductor manufacturing supply chains. Production Planning & Control 22:1, pages 69-80.
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Articles from other publishers (16)
Andreas Haspecker & Lars Mönch. (2023) Exact and Heuristic Algorithms for a bi-criteria Order-Lot Pegging Problem in a Multi-Fab Setting. Exact and Heuristic Algorithms for a bi-criteria Order-Lot Pegging Problem in a Multi-Fab Setting.
Christian Flechsig, Jacob Lohmer, Rainer Lasch, Benjamin Zettler, Germar Schneider & Dietrich Eberts. (2022) Streamlining Semiconductor Manufacturing of 200 mm and 300 mm Wafers: A Longitudinal Case Study on the Lot-to-Order-Matching Process. IEEE Transactions on Semiconductor Manufacturing 35:3, pages 397-404.
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Christian Flechsig, Jacob Lohmer, Rainer Lasch, Benjamin Zettler, Germar Scheider & Dietrich Eberts. (2021) Automated and Optimized Lot-To-Order Matching in 300 mm Semiconductor Facilities. Automated and Optimized Lot-To-Order Matching in 300 mm Semiconductor Facilities.
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Jae-Gon Kim, June-Young Bang, Hong-Bae Jun & Jong-Ho Shin. (2020) Dominance Conditions for Optimal Order-Lot Matching in the Make-To-Order Production System. Processes 8:2, pages 255.
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Jacob Lohmer, Christian Flechsig, Rainer Lasch, Germar Schneider, Dietrich Eberts & Benjamin Zettler. 2020. Digital Transformation in Semiconductor Manufacturing. Digital Transformation in Semiconductor Manufacturing
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J-G. Kim, S-K. Lim, S-O. Shim & S-W. Choi. (2010) Order-lot pegging heuristics for minimizing total tardiness in a semiconductor wafer fabrication facility. Order-lot pegging heuristics for minimizing total tardiness in a semiconductor wafer fabrication facility.
Tsan Sheng Ng, Yang Sun & John Fowler. (2010) Semiconductor lot allocation using robust optimization. European Journal of Operational Research 205:3, pages 557-570.
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Yeong-Dae Kim, June-Young Bang, Kwee-Yeon An & Seung-Kil Lim. (2008) A Due-Date-Based Algorithm for Lot-Order Assignment in a Semiconductor Wafer Fabrication Facility. IEEE Transactions on Semiconductor Manufacturing 21:2, pages 209-216.
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Yang Sun, Andrew Feller, Dan Shunk, John Fowler, Thomas Callarman & Brett Duarte. (2007) Decision Paradigms in the Semiconductor Supply Chain: A Survey and Analysis. Decision Paradigms in the Semiconductor Supply Chain: A Survey and Analysis.
Luke Finlay & Prabhu Manyem. (2006) Online LIB problems: Heuristics for Bin Covering and lower bounds for Bin Packing. RAIRO - Operations Research 39:3, pages 163-183.
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