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International Journal of Computer Mathematics Volume 33, 1990 - Issue 3-4
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Original Articles

A verification of brickell's fast modular multiplication algorithm

Colin D. Walter Computation Department, UMIST, Manchester, M60 1QD, UK
&
Stephen E. Eldridge Computation Department, UMIST, Manchester, M60 1QD, UK
Pages 153-169 | Published online: 19 Mar 2007

Citations (12)

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Read on this site (2)

Stephen E. Eldridge. (1991) A faster modular multiplication algorithm. International Journal of Computer Mathematics 40:1-2, pages 63-68.
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Colin D. Walter. (1991) Fast modular multiplication using 2-power radix. International Journal of Computer Mathematics 39:1-2, pages 21-28.
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Articles from other publishers (10)

Duncan BuellDuncan Buell. 2024. Grundlagen der Kryptographie. Grundlagen der Kryptographie 111 136 .
Duncan BuellDuncan Buell. 2021. Fundamentals of Cryptography. Fundamentals of Cryptography 99 122 .
Nadia Nedjah & Luiza de Macedo Mourelle. (2007) Fast hardware for modular exponentiation with efficient exponent pre-processing. Journal of Systems Architecture 53:2-3, pages 99-108.
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N. Nedjah & Ld.M. Mourelle. (2006) Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic. IEEE Transactions on Circuits and Systems I: Regular Papers 53:3, pages 627-633.
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N. Nedjah & L.M. Mourelle. (2006) HARDWARE ARCHITECTURE FOR BOOTH-BARRETT’S MODULAR MULTIPLICATION. International Journal of Modelling and Simulation 26:3.
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Lejla Batina, Sıddıka Berna Örs, Bart Preneel & Joos Vandewalle. (2003) Hardware architectures for public key cryptography. Integration 34:1-2, pages 1-64.
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N. Nedjah & L. de Macedo Mourelle. (2003) Three hardware implementations for the binary modular exponentiation: sequential, parallel and systolic. Three hardware implementations for the binary modular exponentiation: sequential, parallel and systolic.
Fu-Chi Chang & Chia-Jiu Wang. (2002) Architectural tradeoff in implementing RSA processors. ACM SIGARCH Computer Architecture News 30:1, pages 5-11.
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N. Nedjah & L. de Macedo Mourelle. (2002) Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel. Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel.
S.E. Eldridge & C.D. Walter. (1993) Hardware implementation of Montgomery's modular multiplication algorithm. IEEE Transactions on Computers 42:6, pages 693-699.
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