Citations (12)
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K. Kim, K. K. Das & C.-T. Chuang. (2007) High-density data-retention power gating structure using a four-terminal double-gate device. International Journal of Electronics 94:4, pages 403-412.
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M. S. Alam, T. C. Lim & G. A. Armstrong. (2006) Analog performance of double gate SOI transistors. International Journal of Electronics 93:1, pages 1-18.
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Articles from other publishers (10)
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Marina Reyboz, Olivier Rozeau & Thierry Poiroux. 2009. Planar Double-Gate Transistor. Planar Double-Gate Transistor
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Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang & Kaushik Roy. (2007) Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38:8-9, pages 931-941.
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Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. A. P. Sarab & Sudeb Dasgupta. (2007) Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.
S. Mukhopadhyay, K. Kim, C.T. Chuang & K. Roy. (2006) Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25:10, pages 2052-2061.
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Abhinav Kranti & G. Alastair Armstrong. (2006) Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations. Solid-State Electronics 50:3, pages 437-447.
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Tao Chuan Lim & G. Alastair Armstrong. (2005) Parameter sensitivity for optimal design of 65nm node double gate SOI transistors. Solid-State Electronics 49:6, pages 1034-1043.
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Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang & Kaushik Roy. (2005) Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
S. Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, R.V. Joshi, Ching-Te Chuang & K. Roy. (2005) Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.