A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

Long ZhaoShanghai Research Institute of Microelectronics, Peking University, Shanghai, China;School of Electronics Engineering and Computer Science, Peking University, Beijing, ChinaCorrespondence[email protected]
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Bao LiShanghai Research Institute of Microelectronics, Peking University, Shanghai, China;School of Electronics Engineering and Computer Science, Peking University, Beijing, ChinaView further author information

Yuhua ChengShanghai Research Institute of Microelectronics, Peking University, Shanghai, China;School of Electronics Engineering and Computer Science, Peking University, Beijing, ChinaView further author information

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S. Kazeminia & Sina Mahdavi. (2019) Highly-matched sub-ADC cells for pipeline analogue-to-digital converters. International Journal of Electronics 106:12, pages 1785-1813.
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Articles from other publishers (2)

M. V. N. Chakravarthi & B. Chandramohan. (2022) Calibration of Mismatches in Time-Interleaved ADCs Using Teacher Learner-Based Optimization Algorithm. Journal of Circuits, Systems and Computers 31:09.
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Lei Zhao, Dengquan Li, Henghui Mao, Ruixue Ding & Zhangming Zhu. (2020) A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS. Journal of Circuits, Systems and Computers 30:08, pages 2150143.
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A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

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A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

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