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Original Articles

Novel Flexible Systolic Mesh Architecture for Parallel VLSI Implementation of Finite Digital Convolution

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Pages 261-266 | Received 12 Mar 1996, Published online: 26 Mar 2015

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C.S. Vinitha & R.K. Sharma. (2019) New approach to low-area, low-latency memory-based systolic architecture for FIR filters. Journal of Information and Optimization Sciences 40:2, pages 247-262.
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Articles from other publishers (4)

Payal Paliwal, Janki Ballabh Sharma & Vijay Nath. (2019) Comparative study of FFA architectures using different multiplier and adder topologies. Microsystem Technologies 26:5, pages 1455-1462.
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Grande NagaJyothi & Sriadibhatla SriDevi. (2017) Distributed arithmetic architectures for FIR filters-A comparative review. Distributed arithmetic architectures for FIR filters-A comparative review.
Pramod Kumar Meher, Shrutisagar Chandrasekaran & Abbes Amira. (2008) FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic. IEEE Transactions on Signal Processing 56:7, pages 3009-3017.
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P.K. Meher. (2006) Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution. IEEE Transactions on Circuits and Systems II: Express Briefs 53:8, pages 707-711.
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