https://orcid.org/0000-0001-7896-7164
Citations (5)
Keep up to date with the latest research on this topic with citation updates for this article.
Read on this site (2)
S. Dhanasekar. (2023) An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder. International Journal of Electronics 0:0, pages 1-17.
Read now
Read now
V. Thamizharasan & N. Kasthuri. (2023) FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder. International Journal of Electronics 0:0, pages 1-13.
Read now
Read now
Articles from other publishers (3)
Victor Krasnobayev, Alina Yanko & Dmytro Kovalchuk. (2023) An Improved Method for Performing the Arithmetic Operations of Modulo Addition of the Remainders of Numbers. An Improved Method for Performing the Arithmetic Operations of Modulo Addition of the Remainders of Numbers.
Vishwa Sri Yellu & S. Sreenath Kashyap. (2022) VLSI Implementation of Accuracy Configurable Radix-4 Adder for Digital Image Processing Applications. VLSI Implementation of Accuracy Configurable Radix-4 Adder for Digital Image Processing Applications.
Kaja Naga Venkata Akhil & P. Sathish Kumar. (2022) Implementation of a Low-power N-bit Hybrid Carry Select Adder with Sum-Carry Selection. Implementation of a Low-power N-bit Hybrid Carry Select Adder with Sum-Carry Selection.