A Rail-to-Rail Topology for CMOS Neuron Cells with Analog Inputs-Output and Digital Weights

ABSTRACT

In this article we propose a new CMOS(complementary metal–oxide–semiconductor) neuron topology with analog signals and digital weights. An arrangement of series transconductors multiply the input voltage by the digital weights resulting in weighted currents. These currents can be added or subtracted from the output node. The output current flows through a resistance generating the output voltage. Since the voltage signals are rail-to-rail, the non-linear function of the neuron is naturally obtained by the saturation of the output near ground and supply voltages. The proposed topology is promising for neuromorphic systems as it uses voltage-mode to interconnect different neurons and current-mode for the internal processing (applying a straight-forward computation strategy for neurons). The neuron is designed in CMOS 180 nm, when considering an one-input neuron it occupies and active area of 490 µm${ }^2$ and has a maximum power consumption of 4.7 µW while achieving an operating frequency of 100 kHz. A simple network with three neurons (each one with three inputs) is designed to confirm the proper functionality of the system. The resulting average power per synapse is lower than the one-input cell due to the reduced consumption for some weights and the occupied active area per synapse is also lower because some blocks are not scaled for multiple synapses. On the other hand, the frequency response worsens because the capacitance of the additional input circuits.

KEYWORDS:

• CMOS neuron
• mixed-signal neuron
• rail-to-rail