Design of PFD with free dead zone and minimized blind zone for high speed PLL application

ABSTRACT

In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 $MHz$ − 4 $GHz$ operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 $ps$ in the phase characteristics which improves the output phase noise as −132.9 $dBc/Hz$ at 1 $MHz$ offset frequency. The power consumption is minimised upto 417.3 $\mu W$@ 4$GHz$ operating frequency. The design is simulated in standard 0.18 $\text{mum}$ CMOS technology node with 1.8 $V$ power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication.

KEYWORDS:

• Phase frequency detector
• blind zone
• dead zone
• phase noise
• phase locked loop

Acknowledgement(s)

Authors would like to thank, Ministry of Electronics and Information Technology (MeitY) Govt. of India for providing financial support under SMDP-C2SD Project.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Availability of Data and Material

The authors confirm that the data supporting the finding of this study is available and it will be shared by the corresponding author upon reasonable request.