Design and Suitability Analysis of FPGA-Based TCP/IP Offload Module for Control Systems of FBRs

Abstract

Transmission Control Protocol/Internet Protocol (TCP/IP) offload modules play a crucial role in India’s first commercial fast breeder reactor (PFBR) distributed digital control system architecture by providing networking capabilities to the real-time control systems used in safety-critical and safety-related applications of the PFBR. These modules enable operators to remotely control various mechanisms, facilities, and process loops via real-time control systems from the main control room display stations. The malfunctioning of these modules may hamper the overall plant’s availability; hence to improve further upon safety, security, reliability, and performance, these modules have been indigenously developed for upcoming fast breeder reactors in India. This paper proposes methods to justify the suitability of these communication modules as per the D-25 design guidelines issued by the Atomic Energy Regulatory Board of India.

The design and testing aspects are covered, including an approach toward hardware descriptive language-based design and testing with respect to the IEEE standard and the TCP/IP protocol specifications. Module design validation based on ethernet frame transactions is detailed in this paper. The test platform design, which includes the diagnostics software design for CPUs designed with these TCP offload modules, and the design of a graphical user interface to detect and record TCP connection anomalies are detailed. The network interface response to postulated events of TCP packet corruption, packet drop, packet delay, out-of-order packets, duplicate packets, and heavy traffic is characterized.

Keywords:

• TCP engine qualification
• network impairment
• suitability analysis
• TCP offload module
• request for comment compliance testing

Acronyms

ACK:	=	acknowledgment
ARP:	=	Address Resolution Protocol
DDCS:	=	distributed digital control system
DoS:	=	denial of service
FBR:	=	fast breeder reactor
FPGA:	=	field-programmable gate array
GUI:	=	graphical user interface
HDL:	=	hardware descriptive language
ICMP:	=	Internet Control Message Protocol
IEEE:	=	Institute of Electrical and Electronics Engineers
IP:	=	Internet Protocol
PFBR:	=	prototype fast breeder reactor
RFC:	=	request for comments
RTC:	=	real-time computer
RTL:	=	register transfer level
RTU:	=	remote terminal unit
SoC:	=	system on chip
TCP:	=	Transmission Control Protocol
UDP:	=	User Datagram Protocol
VHDL:	=	very high-speed integrated circuit hardware description language

Disclosure Statement

No potential conflict of interest was reported by the authors.