CMOS Bulk-Controlled Fully Programmable Neuron for Artificial Neural Networks

ABSTRACT

In this paper, the design procedure of a novel neuron is discussed. Starting from the activation function circuit which is based on the modification of regulated cascode structure, a new scheme is presented which can produce the logistic function with high percentage of accuracy. The main advantage of the proposed function generator circuit is its full programmability feature in which its output waveform slope can easily be adjusted by means of the control voltages applied to the bulks of input stage metal oxide semiconductor (MOS) transistors. Also, the output waveform can easily be converted to a step function with the help of bias changes for the input transistors. Following the concepts of the previous work by the authors, the designed activation function has a good compatibility with the employed synapse. Low power and small active-area consumption are the other features of the proposed circuit which qualify it for hardware implementation of neural networks. Post-layout simulation results based on complementary metal-oxide-semiconductor (CMOS) 0.18 µm twin-tub fabrication standard process depict the correct behaviour of the designed circuits and demonstrate 96% accuracy for the proposed activation function structure. The power dissipation of the activation function circuit is 72 µW at the worst case for 1.8 power supply voltage.

KEYWORDS:

• Activation function
• Artificial neural networks
• Compatibility
• Logistic function
• Neuron
• Programmability
• Synapse

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Sarkis Azizian

Sarkis Azizian was born in Urmia, Iran, in 1982. He received his BSc and MSc degrees both in electronics engineering from Urmia University, Urmia, Iran, in 2006 and 2011, respectively. He is currently a PhD degree student of electronics engineering at K. N. Toosi University of Technology, Tehran, Iran.

His research interests are mixed-signal integrated circuit design, hardware implementation of neural networks and fuzzy systems, and digital signal processing.

Viggen Aziz Aghchegala

Viggen Aziz Aghchegala was born in Urmia, Iran, in 1965. He received the BS degree in physics from Isfahan University in 1988, MS degree in solid-state physics from Urmia University in 1996, and PhD degree in physics from Yerevan State University, Yerevan, Armenia, in 2012.

He was formerly an assistant professor at the Islamic Azad University of Urmia Branch from 1997 to 2016 and is currently an assistant professor at Urmia University of Technology, Urmia, Iran.

His research interests are solid-state physics, semiconductor physics, nanostructures, and neural networks.

E-mail: [email protected]

Sarhad Azizian

Sarhad Azizian was born in Urmia, Iran, in 1989. He received the BS degree in mechanics of agricultural machinery from Urmia University in 2013 and the MS degree in mechanics of biosystem from Urmia University, Urmia, Iran, in 2016.

His research interests are alternative and geothermal energies, vermicomposting, and neural networks.

E-mail: [email protected]

Mehdi Sefidgar Dilmaghani

Mehdi Sefidgar Dilmaghani was born in Urmia, Iran, in 1990. He received the BSc degree in electronics engineering from the University of Tabriz, Tabriz, Iran, in 2012 and the MSc degree in electronics engineering from K. N. Toosi University of Technology, Tehran, Iran, in 2016.

He is currently working as researcher at L2S (Laboratory of signals and systems) in the department of electrical engineering of K. N. Toosi University of Technology. His research interests are digital signal processing, FPGA systems, and neural networks.

E-mail: [email protected]