Sub-1 V, 5.5 ppm/°C, High PSRR all CMOS Bandgap Voltage Reference

ABSTRACT

This paper proposes a high power supply rejection ratio (PSRR) voltage reference circuit with a supply voltage ranging from 0.9 to 4 V and fabricated using an SK Hynix 0.18 µm CMOS process. High PSRR is achieved by means of introducing dual PSRR enhancement stages which isolate the bandgap voltage from the variations and noise of the power supply. A temperature coefficient of 5.5 ppm/°C is achieved over a temperature range of 0–125°C, and the power consumption of the circuit is 0.21 µW with a 0.9 V supply at 27°C. The measured PSRR at 100 Hz and 1 KHz is lower than −120 and −100 dB, respectively. The active area of the circuit is 0.0028 mm².

KEYWORDS:

• BGR
• CTAT
• PTAT
• PSRR
• Self-biased op-amp
• Temperature coefficient

Acknowledgements

The author would like to thank IC design education center (IDEC), South Korea for supporting Cadence EDA tools and providing fabrication facility of Multi-Project Wafer (MPW) for Magna Chip /SK Hynix process 0.18 µm.

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Funding

This study was supported by a research fund from Chosun University 2016.

Notes on contributors

Sadeque Reza Khan

Sadeque Reza Khan received BSc degree (2010) in electronics and telecommunication engineering from the University of Liberal Arts Bangladesh and completed his MTech (2014) in VLSI design from National Institute of Technology Karnataka, India. He worked as a research associate in the Department of Information and Communication Engineering at Chosun University, South Korea for two years (2015–2016). Currently, he is pursuing PhD at the School of Engineering and Physical Sciences, Heriot-Watt University, United Kingdom. His research interests include low power VLSI, microelectronics, wireless power transfer, control system design and embedded system design.