Threshold Voltage Modelling of Linearly Graded Binary Metal Alloy Gate Electrode with DP MOSFET

Abstract

Two-dimensional (2D) analytical threshold voltage model for Linearly Graded Binary Metal Alloy (LGBMA) gate electrode with Dielectric Pocket (DP) Metal Oxide Semiconductor (MOSFET) has been developed by solving 2-D Poisson’s equation using evanescent mode analysis technique. In this proposed model, first time the idea of work function engineering is incorporated for DP MOSFET to bring an improvement over different short channel effects (SCEs). In present paper, the expressions for surface potential and threshold voltage are derived along with drain current, transconductance and drain conductance. Moreover, this model also predicts the variations of different SCEs like threshold voltage roll off, Drain-induced Barrier Lowering (DIBL) and sub-threshold swing along the channel length correctly. All analytical results are verified by ATLAS-2D simulator.

Keywords:

• Analytical modeling
• Linearly graded
• Dielectric pocket MOSFETs
• Drain-induced barrier lowering
• Short channel effect
• Sub-threshold slope
• Threshold voltage roll off

ACKNOWLEDGEMENT

Priyanka Saha thankfully acknowledges the financial support as PhD fellow under “Visvesvaraya PhD Scheme”, DeitY, Government of India.

Additional information

Notes on contributors

Priyanka Saha

Priyanka Saha received her BTech degree from Birbhum Institue of Engineering & Technology, WBUT and MTech degree from Jadavpur University. Currently, she is pursuing PhD (Tech.) in the Department of Electronics and Telecommunication Engineering, Jadavpur University under Visvesvaraya PhD Scheme. Her research interests include modelling and simulation of low dimensional devices for improved performance.

Subir Kumar Sarkar

Subir Kumar Sarkar is currently a Professor of Electronics and Telecommunication Engineering Department, Jadavpur University, India. He has completed 18 R&D projects sponsored by different Government of India funding agencies and published more than 590 technical research papers in international/national journals and peer-reviewed conferences. His research interest includes nano devices and low power VLSI circuits, computer networks, digital watermarking and RFID. He is also a senior member of IEEE, IEEE EDS distinguished lecturer, life fellow of IE (India) and IETE, life member of ISTE and life member of IACS. Email: [email protected]