Suppression of Short-channel Effects by Double-gate Double-channel Device Design in Normally-off AlGaN/GaN MIS-HEMTs

ABSTRACT

In this work, we have performed numerical simulations of normally-off AlGaN/GaN recessed Metal–Insulator-Semiconductor or MIS-HEMTs. A double-gate double-channel device design is proposed and analyzed using calibrated TCAD models. The dual-gate geometry is shown to provide an enhanced gate control over the double-channel, thereby suppressing the short-channel effects. The proposed device exhibits 72-mV/decade subthreshold slope, which is 50% improvement compared to the single-gate single-channel device with 3 µm gate length. Both the double-gate double-channel and single-gate single-channel structures are compared for their ability to counter short-channel effects in aggressively scaled MIS-HEMT devices. It is shown that, double-gate design is superior to single-gate single-channel device with 80% improvement in drain-induced barrier lowering at sub-micrometer gate lengths.

KEYWORDS:

• AlGaN/GaN
• double-channel
• double-gate
• MIS-HEMT
• short-channel effects
• subthreshold slope

Disclosure statement

No potential conflict of interest was reported by the authors.

ORCID

Charu Gupta http://orcid.org/0000-0002-8115-3548

Anshul Gupta http://orcid.org/0000-0002-9689-9270

Anil K. Bansal http://orcid.org/0000-0002-6984-2877

Additional information

Funding

This work was supported by the Department of Science and Technology, Government of India, through TSG [grant number DST/TSG/AMT/2015/339] (General).

Notes on contributors

Charu Gupta

Charu Gupta received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Jodhpur, Rajasthan, India in 2016. Currently, she is working towards her Ph.D. degree at IIT Delhi, New Delhi, India. Her research interests include computational and analytical modeling of nanoscale semiconductor devices.

Anshul Gupta

Anshul Gupta received the M.Tech. degree in electrical engineering from Indian Institute of Technology Jodhpur, Rajasthan, India in 2016. He is currently working toward the Ph.D. degree in electrical engineering at IIT Delhi, New Delhi, India. His research interests include design and reliability characterization of semiconductor devices. Email: [email protected]

Anil K. Bansal

Anil K. Bansal (S’17) received the M.Tech. degree from the National Institute of Technology Hamirpur, India, in 2013. He is currently pursuing the Ph.D. degree with the Department of Electrical Engineering, IIT Delhi, New Delhi, India. His research interests include sub-10 nm logic CMOS device design and characterization. Email: [email protected]

Abhisek Dixit

Abhisek Dixit (SM’13) received the Ph.D. degree from the Katholieke University of Leuven, Leuven, Belgium, in 2007. He is currently an Associate Professor with the Department of Electrical Engineering at IIT Delhi, New Delhi, India. His current research interests include nanoscale CMOS device design and process technology, reliability, radiation hardness, and GaN HEMT device modeling. He has 6 US patents and more than 40 publications in international conferences and journals. Email: [email protected]