A Novel Design of 12-bit Digital Comparator Using Multiplexer for High Speed Application in 32-nm CMOS Technology

Abstract

In the present scenario, power, speed, and area of an electronic device play a significant role specifically in the field of modern VLSI technology. In this research, small power dissipation and a less area-based single 12-bit comparator has been designed using a multiplexer. To improve the speed of the comparator a completely unique technique has applied, where three 4-bit comparator blocks have been used rather than a single 12-bit comparator. These comparator blocks compare simultaneously two signals each having 4-bits. The aim of this paper is to design and implement a 2-bit digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. Finally, the novel technique has been applied to improve the overall performance of a 12-bit comparator. The results of this paper are simulated on the EDA tanner tool realized in 32-nanometer technology at 0.7 V supply voltage. It shows that the propagation delay of 12-bit digital comparator using the novel technique is 5.15 nanoseconds which is approximately 30% less than the proposed multiplexer-based single 12-bit comparator.

KEYWORDS:

• Conventional CMOS
• Digital comparator
• Multiplexer-based comparator
• Power dissipation
• Propagation delay
• Transistor count
• Transmission gate logic technique

Acknowledgment

The authors are thankful to the faculties of ECE dept, Bankura Unnayani Institute of Engineering for giving useful advice.

Additional information

Notes on contributors

D. N. Mukherjee

Dwip Narayan Mukherjee had been awarded MTech in ECE from Burdwan University, Burdwan, India. He is currently working as assistant professor in Electronics and Communication Engineering Department of Bankura Unnayani Institute of Engineering, WB, India. His research interest is in the area of VLSI low power design, image processing, signal processing. Corresponding author. Email: [email protected]

S. Panda

Saradindu Panda has been serving as HOD of Electronics and Communication Engineering Department of Narula Institute of Technology, Agarpara, Kolkata for nine years. He has received PhD in ECE from NIT, Durgapur in 2014. He has received his BE degree in ECE from UIT, Burdwan University in 2004 and MTech degree in VLSI and microelectronics technology from Jadavpur University in 2007. He is also a National Scholarship winner in his school level. He is a professional member of IEEE, professional member of IET, institutional member of IETE. His research interests include low power and high speed VLSI circuit design, noise modelling and analysis of advanced semiconductor devices like DGMOSFET, SGMOSFET, MESFET, HEMT etc, Design of SOCs, VLSI signal processing, advanced digital system design and embedded system design. He has published one Book on “Microelectronics and Optoelectronic Devices” Devices and more than 30 research articles in peer-reviewed international journals, national and international conferences. Email: [email protected]

B. Maji

Bansibadan Maji is now a senior professor of ECE Department in NIT, Durgapur, West Bengal, India. He is now head of the Department of ECE at NIT. His main research area is on microwave, antenna, VLSI design and low power device and circuits. He has more than 56 publications in different international and national journals and conference proceedings. He has published more than 50 research articles in peer-reviewed international journals, national and international conferences. Email: [email protected]