Novel Quaternary Quantum Reversible Half Adder and Full Adder Circuits

Abstract

One of the major problems in designing highly compact digital systems is the rate of power consumption and internal heat generated by the loss of information during the computation. The tendency of current circuit design technologies is towards Nanoscale. Quaternary reversible logic is an emerging technology for the future designing of the quantum systems since quantum reversible circuits can be realized in Nanoscales. The adder building block is an essential part of any computer system. This block must be designed efficiently. We proposed a new quaternary quantum reversible half adder with the quantum cost of 17 and a quaternary quantum reversible full adder with a quantum cost of 23. For the first time in the literature, we report that we proposed quaternary quantum reversible half adder as well as full adder with an optimum number of constant inputs. As the circuit lines in the domain of quantum computation are considered to be a very limited resource, the achievements in this paper are promising. The proposed circuits are efficient in terms of all figures of merits in comparison to the existing counterparts. To design these adder circuits, we used 1-qudit and 2-qudit quaternary gates.

KEYWORDS:

• Adders
• Multiple-valued logic
• Quantum computing
• Quantum reversible adder
• Quaternary reversible adder
• Reversible logic

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Abdollah Norouzi Doshanlou

Abdollah Norouzi Doshanlou received his MSc degree in computer architecture from Faculty of Technical & Engineering, Department of Computer Engineering, Tabriz Branch, IAU University, Tabriz, Iran. He is currently a PhD candidate in computer architecture at Science and Research Branch, Islamic Azad University. He is working on multi-valued quantum reversible circuit design. Email: [email protected]

Majid Haghparast

Majid Haghparast received his BSc in computer hardware engineering in 2003. He received his MSc and PhD degrees in computer architecture in 2006 and 2009, respectively. Since 2007, he has been affiliated with the Computer Engineering Faculty, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, IAU University, Tehran, Iran. He is currently an associate professor and the head of the computer engineering department at Electrical and Computer Engineering Faculty, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, IAU University, Tehran, Iran. He has also been selected as his university's best researcher in 2017. Majid has published more than 50 research papers in various international journals and conferences. His research interests include cloud computing, WSNs, reversible logic, and computer arithmetic. Since April 2017 he is conducting his sabbatical at the Johannes Kepler University Linz, Austria, where he also is a research fellow. He served in more than 40 international conference advisory and technical program committees. Dr Haghparast is on the panel of reviewers for various international journals. Corresponding author. Email: [email protected]

Mehdi Hosseinzadeh

Mehdi Hossein-Zadeh, received his BS degree in computer hardware engineering, from Islamic Azad University, Dezfol branch, Iran in 2003. He also received his MSc and the PhD degrees in computer system architecture from the Science and Research Branch, Islamic Azad University, Tehran, Iran in 2005 and 2008, respectively. He is currently an associate professor in Iran University of Medical Sciences (IUMS), Tehran, Iran, and his research interests include SDN, information technology, data mining, big data analytics, E-commerce, E-marketing, and social networks. Email: [email protected]