Test Pattern Generator for MV-Based QCA Combinational Circuit Targeting MMC Fault Models

Abstract

Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit Technology considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology. Being at molecular scale, defects are more likely to occur in QCA devices. Therefore, the substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. This paper addresses the fault model caused by multiple missing cells defect and test generation for these faults for QCA circuits. We have shown that the single missing cell considerations are not enough. Correspondingly, in this paper, testing properties for the detection of fault caused by multiple missing cell defects in QCA devices mainly Majority Voter (MV) are proposed. Even though there are many advanced ATPGs available for CMOS technology, to demonstrate very special MV-based properties with reference to the test pattern generation process and to open the path for advanced combinational and sequential ATPGs specific to MV-based QCA circuits, the extension of basic Automatic Test Pattern Generator is proposed here. The proposed test generation algorithm is guided by the extended Sandia Controllability Observability Analysis Program (SCOAP) testability measures especially for QCA logic primitives.

KEYWORDS:

• ATPG
• Defect
• Fault model
• Multiple missing cells
• Majority voter
• QCA
• Testability measures

Additional information

Notes on contributors

Vaishali Dhare

Vaishali Dhare has been working as an assistant professor in Electronics and Communication Engineering Department, Institute of Technology, Nirma University, Ahmedabad since 2004. She has more than 18 years of academic experience. She obtained her BE degree in electronics and telecommunication engineering in 2000 from North Maharashtra University, Maharashtra and post MTech in VLSI design in 2010 from Nirma University, Ahmedabad. Vaishali obtained her PhD in VLSI design in 2018 from Nirma University, Ahmedabad. Her area of interest includes testing and verification of VLSI design, quantum-dot cellular automata, applied algorithms for VLSI CAD, reversible logic, and hardware description languages. She has published more than 15 papers in journals and conference proceedings. She is a member of IEEE, Life Member of ISTE and VSI. Email: [email protected]

Usha Mehta

Usha Mehta is currently working as a professor in Electronics and Communication Engineering Department, Institute of Technology, Nirma University, Ahmedabad. She has more than 24 years of experience including industry and academic experience. She received her BTech and MTech degree in electronics and communication engineering and the PhD degree in VLSI design in 1994, 2005, and 2011, respectively. She has authored one book and over 55 research papers in the area of VLSI testing, digital VLSI design, hardware security and testing of emerging technologies. She has successfully executed two research projects funded by ISRO and GUJCOST. She has one patent to her credit. She has delivered a number of technical talks at various conferences and workshops. She is guiding six research scholars towards doctoral program. She has contributed as the conference chair of international conferences VDAT’2015 and NUiCONE’2012. She is chairing the IEEE Gujarat Section's Women-In-Engineering Affinity Group. She is a senior member of IEEE, Associate member of CSI, Senior Member of IETE and Life member of ISTE. Corresponding author Email: [email protected]