Superior Transient Response to Heavy-Ion Irradiation by N-Channel SOI-iFinFETs

Abstract

In this paper, we for the first time report the transient response of SOI-iFinFETs under heavy-ion radiation conditions. Using calibrated 3-D TCAD simulations, we analyze the radiation performance of advanced multi-gate devices such as SOI-FinFET and iFinFETs, which conform to 14 nm technology node. The transient response of FinFETs, and iFinFETs with varying number of inserted oxide regions, is reported under heavy-ion irradiation. The effective fin width and gate length scaling has also been reported for FinFET and iFinFETs under heavy-ion irradiation. Our results show that iFinFETs are better suited for heavy-ion radiation environments as compared to FinFETs due to the presence of inserted oxide in between the fin regions. The iFinFETs show up to 28% less peak drain current generated due to heavy-ion with LET = 10 MeV-cm²/mg as compared to FinFETs. We also show that iFinFET architecture brings more advantage to radiation performance over conventional FinFETs for narrow fin devices, while gate length scaling has similar radiation response for both FinFET and iFinFETs.

Keywords:

• Collected charge
• FinFET
• Heavy-ion
• iFinFET
• Irradiation
• MOSFETs
• Radiation response
• Silicon-on-Insulator
• TCAD (Technology Computer Aided Design)

Additional information

Funding

This work was partially supported by the Science and Engineering Research Board, Government of India [grant number CRG/2018/003974] and Visvesvaraya Young Faculty Research Fellowship of Ministry of Electronics and Information Technology, Government of India.

Notes on contributors

Kritika Aditya

Kritika Aditya received the BE degree from NSIT, Delhi University, India, in 2011, and the MTech degree from CDAC-Noida, GGSIPU, Delhi, India, in 2014. She is currently pursuing the PhD degree with Department of Electrical Engineering, IIT Delhi, India. Her current research interests include radiation characterization of semiconductor devices and embedded memories. Corresponding author. Email: [email protected]

Ramendra Singh

Ramendra Singh received the MTech degree from the Indian Institute of Technology Delhi, India, in 2013. He also received the PhD degree in electrical engineering at IIT Delhi India, in 2019. His research interests include RF characterization and modeling of the state of the art semiconductor devices. Email: [email protected]

Anil Kumar Bansal

Anil K Bansal received the PhD degree from the Department of Electrical Engineering, IIT Delhi, New Delhi, India, in 2018. He completed the MTech degree from the National Institute of Technology Hamirpur, India, in 2013. He is currently working as a compact device modeling engineer at Intel, Bangalore. His research interests include sub-10 nm logic CMOS device design, characterization and modeling. Email: [email protected]

Rohit Saini

Rohit Saini received his BTech degree from Indian Institute of Technology Delhi, India in 2019. Email: [email protected]

Anshul Gupta

Anshul Gupta received the MTech degree in electrical engineering from Indian Institute of Technology Jodhpur, Rajasthan, India in 2016. He is currently working toward the PhD degree in electrical engineering at IIT Delhi, New Delhi, India. His research interests include design and reliability characterization of semiconductor devices. Email: [email protected]

Abhisek Dixit

Abhisek Dixit is currently an associate professor in the Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, INDIA. Other positions he held prior to this include assistant professor of electrical engineering at IIT Delhi and advisory research engineer at IBM SRDC. Dr Dixit received his PhD from KU Leuven/IMEC Belgium in 2007 and MTech from IIT Bombay, India in 2002. He has worked on fabrication, characterization, compact and TCAD modeling of devices and circuits on various 300 and 200-mm technologies, including bulk Si, PD and FD-SOI, BiCMOS. Although his modeling and characterization work spans range of technology nodes all the way from 10-nm up to 0.35-micron, in his early career he focused on SOI-FinFET device-technology integration at 45, 32, 14-nm nodes. His current research interests include silicon based quantum computer technology, CMOS reliability including hot-carrier degradation and radiation hardness, pulsed/RF characterization and modeling of logic devices, and device scaling of SOI, nanowire, nanosheet, and negative capacitance-FETs beyond 7-nm nodes. Dr Dixit has more than 70 publications and 4 patents in FinFET and related technologies. He is currently an EDS distinguished lecturer, senior member of IEEE, and recipient of MeitY young faculty research fellowship. Email: [email protected]