Design and Analysis of 2.4 GHz Low-Noise, High-Gain 0.18 μm CMOS Cascode Low-Noise Amplifier for IRNSS Applications

Abstract

Low-Noise Amplifier (LNA) plays a crucial part in Radio Frequency (RF) front-end architecture. This paper mainly focuses on designing LNA for Indian Regional Navigation Satellite System (IRNSS) receiver. IRNSS operates on two frequency bands (L5 and S band) and this design is proposed for S band with the center frequency of 2492.028 MHz. Cascode topologies are considered to be conventional ones and they provide higher gain and better reverse isolation. Four different approaches of single-stage cascode topology, such as Common Source (CS) cascode, Common Gate (CG) cascode, shunt-resistive feedback cascode and current reuse cascode, were designed and their performance metrics, based on gain, Noise Figure (NF), return losses and stability, are presented. Focused on the gain and noise figure improvements, Common Source (CS) cascode with interstage series LC circuit LNA was designed and optimized with input and output matching circuitries. The proposed optimized circuit uses current reuse technique along with CS stage to improve the power gain and to achieve low-noise figure. The interstage LC circuit is mainly implemented to act as a tuning circuit to achieve a narrow range of frequency. The proposed work is simulated using 180 nm CMOS technology Generic Process Design Kit (GPDK) and achieve a power gain (S21) of 24.89, 0.994 dB NF, −16.2 dB input return loss (S11) and −11.06 dB output return loss (S22), with higher reverse isolation around −30.47 dB at 1.8 V power supply.

Keywords:

• ADS
• Generic PDK
• IRNSS
• LC network
• Low-noise amplifier
• RF CMOS

Acknowledgement

The authors would like to thank Indian Space Research Organization (ISRO) for funding this project (Ref: ISRO/RES/4/654/18-19).

Additional information

Funding

This work was supported by Indian Space Research Organisation [Grant Number ISRO /RES/4/654/18-19].

Notes on contributors

D. Jahnavi

D Jahnavi received the BE degree in electronics and communication engineering and the ME degree in applied electronic from Anna University, Chennai, TN, India, in 2010 and 2013, respectively. She is currently pursuing PhD degree in information and communication engineering at Anna University, Chennai, TN, India. She is working as a research fellow in S A Engineering College for a project funded by Indian Space Research Organization (ISRO). Her current research interests include CMOS RF/microwave integrated circuits, IC fabrication.

G. Kavya

G Kavya received the BE degree in electronics and communication engineering in 1999 from the Govt College of Engineering, Salem, affiliated to Madras University and the ME degree in electronics engineering in 2003 from MIT, Anna University. She has received her PhD from Sathyabhama University in electronics engineering in 2015. She is currently working as a professor in the Department of Electronics and Communication Engineering, S A Engineering College, Chennai. She has 20 years of teaching experience in handling UG and PG classes. She has guided many BE and ME projects. She is also guiding PhD research scholars. Her areas of interest include VLSI, microwaves and signal processing. She has contributed to many papers in national and international journals. She is a member of ISTE, IETE and IEEE. She is currently working on a project funded by Indian Space Research Organization (ISRO) as the principal investigator. Email: [email protected]

Anjana Jyothi Banu

Anjana Jyothi Banu received the BE degree in electronics and communication engineering and the ME degree in communication systems from Anna University, Chennai, TN, India, in 2010 and 2013, respectively. She is currently working as an assistant professor, ECE Department in S A Engineering College. Her interests include CMOS RF/microwave integrated circuits, wireless communication and microwave engineering. She is an active member of IEEE Photonic Society and IETE. Email: [email protected]