Sensitivity of SET Pulse-Width and Propagation to Radiation Track Parameters in CMOS Inverter Chain

Abstract

Single-event transient (SET) due to heavy-ion strike is a serious reliability concern for devices operated in radiation environment. Due to technology scaling, nodal capacitance decreases which increases the SET vulnerability. In this paper, the sensitivity of SET pulse width in 45 nm bulk and SOI MOSFET to linear energy transfer (LET), heavy-ion track length, angle of strike, characteristic radius, and characteristic time of the track is analysed. The modification of SET pulse width while propagating through 45 nm bulk-and SOI-based CMOS chain of inverters and its dependence on aforementioned radiation parameters is also analysed. The results show that all the pulses produced in SOI-based inverter chain get attenuated during propagation and do not reach the last stage. However, in the case of bulk, any SET having pulse width greater than 37 ps (measured using full width at half maximum) propagates and reaches the last stage of the inverter chain. Thus, the SOI devices are more immune to SET compared to the bulk, for different heavy-ion track parameters.

Keywords:

• Heavy-ion
• CMOS inverter chain
• Pulse width
• Pulse propagation
• Single-event transient

ACKNOWLEDGEMENTS

The authors would like to thank the Department of Science and Technology (DST), Government of India for its financial assistance (grant no. SERB/F/6724/2018-19) in carrying out these research activities.

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Funding

This work was supported by Science and Engineering Research Board [SERB/F/6724/2018-19]

Notes on contributors

K. R. Pasupathy

K R Pasupathy completed ME in VLSI Design from Anna University and PhD degree from VIT Chennai. He worked as assistant professor in SKP Institute of Technology. He is currently working as post doctoral researcher in NIT, Trichy. His research interests are reliability issues due to radiation in CMOS VLSI circuits. E-mail: [email protected]

B. Bindu

B Bindu completed MTech from CUSAT, Kerala and PhD degree from IIT, Madras. She worked as a post-doctoral researcher in Device Modeling Group, University of Glasgow, UK and in the Institute for Microelectronics, TU Vienna, Austria. Currently, she is working as an associate professor in VIT Chennai. Her research interests are semiconductor device modelling and analog circuit design.