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Articles

Analysis of Ethernet Control Network

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Pages 1588-1596 | Published online: 22 Jan 2021
 

Abstract

Building a reliable communication network is a challenging task using the standard Ethernet as the medium for control and data acquisition networks. Such sensor-actuator networks could be distributed across multiple locations across a building. Packet retransmissions and losses could be critical when Ethernet is used for closed-loop controls and measurements. There could be multiple design challenges to build such networks such as total-traffic, compact node design, bandwidth limitations, packet retransmissions, delays, drops etc. In this paper, we report how we implemented a reliable http-based automation network of large interconnected microcontroller-based nodes with a careful design of hardware, firmware components and a new application-layer faulty-node-filter-algorithm. It analysed some of the top causes of poor network performance within such control networks using a popular network protocol-analyser “Wireshark”. Though Ethernet seemed the most future promising, it has the single drawback of nondeterministic packet transfers. Additional research is carried out to prove that IEEE 802.3 standard Ethernet could be used in applications like our slow-cryogenics-control systems of linear Accelerators to build an error-free, near deterministic control-application. This approach allowed the continued use of conventional Ethernet networking components. even for the control networks and the same communication medium. The tested system is distributed within a private LAN of more than 50 embedded servers each of which is built out of on-chip TCP/IP stacks implemented on ARM processors as nodes, for a successfully implemented Cryogenic control network of Superconducting linear Accelerator at Inter University Accelerator Centre, New Delhi, India.

Acknowlegements

The authors would like to acknowledge all the members of Cryogenics group of IUAC who played active role in setting up the mechanical systems of cryogenics required for linear accelerator. The authors acknowledge Director, IUAC, New Delhi for his support.

Additional information

Notes on contributors

Joby Antony

Joby Antony received the Bachelor’s degree in electronics and communication engineering from Faculty of Engineering, Jamia Millia Islamia (JMI Central University), New Delhi, masters in electronics & computer technology from Kent State University, USA and PhD from Indian Institute of Technology (ISM), Dhanbad, Jharkhand, India. He is working as engineer-F at Inter University Accelerator Centre, Formerly Nuclear Science centre, a reputed research centre of University Grants Commission, New Delhi, India in hardware, firmware and software design related to embedded control systems. He has been a visiting scientist to CERN in LHC instrumentation & control-related activities.

Tanmoy Maity

Tanmoy Maity received his graduation and master’s degree in electrical engineering from Calcutta University and PhD from Bengal Engineering & Science University, Shibpur. He has six years industrial and more than twenty years academic experience. He is currently working as associate professor in Indian Institute of Technology (ISM), Dhanbad, Jharkhand, India. Email: [email protected]

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