MVSI and AVSI-supported DSTATCOM for PQ Analysis

ABSTRACT

This paper presents a dual voltage source inverter (DVSI)-based Distributed Static Compensator (DSTATCOM) to enhance the power quality in the power utility system (PUS). The proposed DSTATCOM consists of two numbers of two-level voltage source inverters (VSI) which controls the reactive power. One of them is regarded as the main voltage source inverter (MVSI) and the other is considered as auxiliary voltage source inverter (AVSI). The $i\cos \varphi$ control algorithm is employed to generate the reference source currents as well as switching pulses. The detailed control algorithm is formulated by mathematical analysis using MATLAB/Simulink, and compared with different case studies. Among all the theoretical findings, the DVSI offers better voltage regulation, voltage balancing, source current harmonic reduction and power factor correction under various loading scenarios. Apart from these, reliability, stress balancing of the both MVSI and AVSI, cost reduction due to a decrease in the filter size and better operation of PUS is obtained. To check the effectiveness, the performance of the DVSI-based DSTATCOM is carried out as per the benchmark value of the IEEE-519-2014 and IEC-61000-1 grid code.

KEYWORDS:

• AVSI
• DSTATCOM and PQ
• $i\cos \varphi$
• Control algorithm
• MVSI

Additional information

Notes on contributors

Mrutyunjaya Mangaraj

Mrutyunjaya Mangaraj received the BTech (Hons) in electrical engineering from Berhampur University, India, in 2006. He received the MTech in power system engineering from VSSUT, Burla, India, in 2010. He served as an assistant professor in the Department of Electrical Engineering at NIST Berhampur, India, from 2010 to 2013. He obtained PhD from National Institute of Technology, Rourkela, in 2018. He rejoined at NIST Berhampur for 1.5 years and currently continuing as an associate professor in the Department of Electrical and Electronics Engineering at LIET Vizianagaram. He is associated as the principal investigator in SERB sponsored project under the SRG grant. His areas of research interest include power system economics, design and modelling of d-FACTS devices with embedded controller, soft computing techniques etc. Email: [email protected]

Jogeswara Sabat

Jogeswara Sabat received the BTech in electrical and electronics engineering from BPUT, India, in 2016. He received the MTech in power system engineering from PMEC, India, in 2019. He is currently working as a senior research fellow in EEE Department of LIET Vizianagaram under DST/SERB project. His area of research interest includes power quality, design and modelling of custom power devices etc.