Design of Dual-Delay-Path Low-Power VCRO with I-MOS Varactor Tuning

Abstract

This paper presents a novel low-power four-stage voltage controlled ring oscillator (VCRO) designed in the TSMC 180 nm CMOS technology. Each stage in the proposed VCRO consists of a differential delay cell. Output frequency tuning is controlled by the I-MOS varactor connected at the output of each delay stage. Different performance parameters, including tuning range, power consumption, phase noise and figure of merit, have been obtained in the TSMC 180 nm CMOS technology. Results show that the output oscillation frequency of VCRO is tunable from 0.545 to 1.195 GHz by varying the drain/source voltage (V_ids) from 0.6 to 1.8 V with a supply voltage (V_dd) of 1.8 V. Furthermore, it provides a wide tuning range from 0.152 to 1.903 GHz with the variation in V_dd from 1 to 3 V with different I-MOS widths of 0.5, 1, 2 and 4 µm. Furthermore, effects of change in V_ids from 0.8 to 1.8 V with V_dd variations from 1 to 3 V have been evaluated with I-MOS varactor width (W) of 2 µm. Frequency range from 0.170 to 1.451 GHz has been achieved for this tuning method. The proposed VCRO exhibits the phase noise of −100.45 dBc/Hz @1 MHz and −96.01 dBc/Hz @0.6 MHz from the centre frequency with power consumption 0.003 to 3.165 mW with a change in V_dd from 1.8 to 3.0 V. The figure of merit (FoM) of the proposed VCRO is 161.77dBc/Hz.

KEYWORDS:

• Delay cell
• I-MOS varactor
• Low power
• VCO
• Voltage tuning
• XNOR gate

Additional information

Funding

The authors would like to acknowledge the support provided by Young Faculty Research Fellows (YFRFs) of Visvesvaraya PhD Scheme Ref: DIC/MUM/GA/10(37) D.

Notes on contributors

Manoj Kumar

Manoj Kumar is working as an associate professor in USICT (ECE), GGSIP University, Dwarka, New Delhi. He has more than 17 years of experience in teaching and research. He has published 45 research papers in international/national journals. He has also published more than 40 research papers in international/national conferences. His research interests include integrated circuit design, low power CMOS systems and microelectronics for communication systems. He is Life Member of IETE (India), ISTE (India), CSI (India) and Semiconductor Society of India. He received Young Faculty Research Fellowship from Digital India Corporation, Ministry of Electronics and Information Technology, Govt of India in 2019. Email: [email protected]

Dileep Dwivedi

Dileep Dwivedi is working as an assistant professor in USICT (ECE), GGSIP University, Dwarka, New Delhi. He is presently doing the research work in the field of low power CMOS circuit design. He has published 04 SCI/SCIE research papers in the international journals. He has also published 2 research papers in international conferences. His research interests include integrated circuit design, low-power CMOS systems and analog signal processing.