Optimization of Discrete Anamorphic Stretch Transform and Phase Recovery for ECG Signal Compression

Abstract

An ECG signal compression scheme using both Discrete Anamorphic Stretch Transform (DAST) and Discrete wavelet transform (DWT) is reported in the literature. In this scheme, a linear filter is used for the recovery of the phase of the DAST for the computation of inverse DAST. However, at a higher compression ratio, the phase recovered and the reconstructed signal became increasingly inaccurate. To overcome this problem, a phase recovery technique that uses only an adder with fixed offset is proposed in this paper. A scheme for optimizing the DAST kernels to increase the compression ratio is also proposed. To evaluate their effectiveness, the ECG signals of the MIT-BIH Arrhythmia database are compressed using 6 level 1D DWT and run-length encoding with and without DAST pre-compressor and their performances are compared. The phase of DAST of the ECG signals recovered using both linear filter and adder are computed and compared for different kernels. The proposed phase recovery scheme with the optimized sublinear and linear kernels provides a 12.2% and 10.91% increase in data compression ratio and 24.63% and 28.73% decrease in percentage root mean square difference (PRD) with 99.9% of energy packing efficiency (EPE) compared to the scheme using the filter. The compression scheme using DAST provides a 2.81 times higher compression ratio compared to that without DAST. The proposed compression scheme yields a higher Compression Ratio and lower PRD than those reported in the literature. It can be used as pre-compressor for the real time transmission of ECG signal with lower bandwidth.

KEYWORDS:

• Complex transform
• Compression
• Discrete anamorphic stretch transform
• Electrocardiogram
• Occupied bandwidth
• Phase recovery

DATA AVAILABILITY STATEMENT

The data used to support the findings of this study are publically available and cited in [40].

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

R. Thilagavathy

Thilagavathy received BE degree in electronics and communication engineering from Madras University, Chennai, India, in 1998, and ME degree in VLSI systems from National Institute of Technology, Trichy (Formerly known as Regional Engineering College, Trichy), India in 2000. She joined National Institute of Technology, Trichy as research associate in 2000 and has been working as assistant professor in the Department of Electronics and Communication in NIT Trichy since 2006. She is presently pursuing PhD in biomedical signal processing and applications. She has published many papers in international and national conferences. Her research interests include Embedded system design, low power VLSI system design, biomedical signal processing and IoT applications. She has guided many projects in the design and implementation of systems in these areas on FPGA and embedded platforms.

B. Venkataramani

B Venkataramani received the BE degree in electronics and communication engineering from Regional Engineering College, Tiruchirappalli, India, in 1979 and the MTech and PhD degrees in electrical engineering from Indian Institute of Technology, Kanpur, India, in 1984 and 1996, respectively. He worked as Deputy Engineer in Bharath Electronics Ltd, Bangalore, India, and as a research engineer in the Indian Institute of Technology, Kanpur each for approximately 3 years. Since 1987, he has been with the faculty of the National Institute of Technology, Trichy (Formerly known as Regional Engineering College, Trichy). Currently, he is the professor of the Electronics and Communication Department. He has published two books and numerous papers in journals and international conferences. His current research interests include design of DSP systems on field-programmable gate array (FPGA), system on chip (SOC) design and design of analog and mixed signal VLSI systems. Email: [email protected]