A Low Power Voltage Spike Detection Circuit for Cap-less LDO

ABSTRACT

A low-power voltage spike detection (VSD) circuit for a cap-less low-dropout regulator (LDO) is presented in this paper. The LDO is based on the cascoded flipped voltage follower (CAFVF) topology, and the transients in the output voltage are controlled by the spike detection circuits and these circuits get activated only during the transient period. The overshoot voltage spike detection (OVSD) circuit senses the output voltage via intermediate voltage $V_X$ and reduces the current through the power MOSFET by charging the gate capacitance $C_P$ and restores the output voltage whenever the output voltage rises. The undershoot voltage spike detection (UVSD) circuit directly detects the output voltage and increases the current through the power MOSFET by discharging the gate capacitance $C_P$ and restores back the output voltage whenever the output voltage drops. The VSD circuit consumes only a bias current of $9\hspace{0.17em}\mu A$ in the steady state. This LDO is implemented in $180nm$ CMOS technology and achieved a good load transient response with $500\hspace{0.17em}ns$ settling time with the maximum voltage spike of $250\hspace{0.17em}mV$ over the load current range of $100\hspace{0.17em}\mu A$ to $50\hspace{0.17em}mA$.

KEYWORDS:

• Low-dropout regulator
• flipped voltage follower
• transient response
• voltage spike detection circuits
• settling time
• system-on-chip (SoC)

Disclosure statement

No potential conflict of interest was reported by the author(s).