Network interface for NoC based architectures

Abstract

The emergence of the network on chip (NoC) as a communication backbone for system on chip (SoC) based designs requires standardized interfaces for integrating intellectual property (IP) cores with diverse communication requirements. These interfaces have to be simple and generic for rapid plug and play implementation with minimal overhead. In this paper, we describe the design and implementation of a programmable fabric based network interface architecture. We have also developed a controller for a memory unit that handles memory block allocation of multiple aspect ratios. This facilitates the integration of cores of diverse data widths and memory requirements. We have mapped the Joint Photographic Experts Group (JPEG) compression application on our architecture to demonstrate the feasibility of our design. The network interfaces seamlessly connect existing IP modules (processor core, JPEG core, memory core and Universal Asynchronous Receiver Transmitter (UART) core) to the NoC. The network, IP cores and the network interfaces are implemented on an Field Programmable Gate Array (FPGA) device. The behavioural implementation of various cores and the NoC is captured using Verilog and VHDL. We show experimentally that the overhead introduced due to network interface is not substantial for computation intensive cores.