Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval

Abstract

With ever larger and more affordable storage capabilities, individuals and companies can now collect huge amounts of multimedia data, especially images. Searching such databases is still an open problem, known as content-based image retrieval (CBIR). In this paper, we present a hardware architecture based on FPGAs which aims at speeding-up visual CBIR. Our architecture is based on the unique combination of reconfigurable resources and flash memory, allows for a speed-up factor of 45 as compared to existing software solutions.

Keywords:

• high performance computing
• image processing
• reconfigurable architecture

Notes

Note

1. Note that the software implementation takes advantage of this property to skip distance calculation whenever the current score is above its corresponding k-NN list threshold score.