Voltage lowering and gain control techniques for a single-supply-driven 0.7 V amplifier

Abstract

A CMOS amplifier architecture is presented with a voltage lowering technique so that it can be driven from a single 0.7 V bias supply. The topology does not need scaled gate voltages (or additional bias circuits) and uses branching of its bias path to reduce power requirement. A three-stage cascaded structure is adopted for high gain with the output common-drain block realizing a gain control mechanism. The technique achieves 6 dB gain regulation (with a control voltage) at the expense of small additional power (1.27 mW). A K-band architecture is simulated with a 90-nm CMOS process to verify the proposed mechanisms. The low-power (7.37 mW) unregulated front-end achieves $>$27 dB gain with a noise figure range of 2.99–3.06 dB within the 20.5–22.2 GHz bandwidth. Port reflection loss figures ($S_{11}$ and $S_{22}$) are analysed to be $<$−8 dB and $<$−11 dB. The circuit has an area requirement of 0.62 mm² and performs better in terms of power supply requirement and potential packaging cost when compared with simulated results of published millimetre-wave amplifiers.

Keywords:

• single-supply amplifier
• gain control
• voltage lowering technique
• CMOS

Acknowledgment

The authors would like to appreciate the guidance provided by the faculty of Department of EEE of Bangladesh University of Engineering and Technology.