A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder

ABSTRACT

Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currents$I_{on}$ and one-tenth the off-currents $I_{off}$ than the equally sized MOSFETs at the same technology node, making them ideal candidates for ultra-low-power VLSI applications. This paper presents a complementary GOTFET (CGOT) based dynamic full adder (DFA), which consumes significantly lower power than conventional CMOS DFAs and operates at double the speed of CMOS DFAs. A conventional DFA designed using GOTFETs instead of MOSFETs exhibits 100 ps (40%) lower & 50 ps (30%) lower delays than CMOS DFA. Furthermore, the CGOT DFA consumes merely 2.6 pW of static power, which is 99% (2 orders) lower than the corresponding CMOS DFA ., $I_{on}$, . This paper proposes a novel improved DFA circuit design, which mitigates the dynamic power by eliminating redundant switching activity within the DFA circuit, . The proposed modified DFA topology reduces the total power consumption by 25% than the conventional DFA designs at 50% switching activity. The overall power delay product (PDP) reduces to merely 0.9% of the standard CMOS designs. The total power consumption reduces even further with decreasing switching activity, and the improved CGOT DFA consumes 31% lower total power (at 25% switching activity).

KEYWORDS:

• Full adder
• 45 nm CMOS technology
• I_on:I_off ratio
• power delay product
• nanoscale GOTFET
• verilog-A

Disclosure statement

No potential conflict of interest was reported by the authors.