Minimizing total weighted tardiness on a batch-processing machine with incompatible job families and job ready times

Abstract

Semiconductor wafer fabrication facilities (“wafer fabs”) strive to maximize on-time delivery performance for customer orders. Effectively scheduling jobs on critical or bottleneck equipment in the wafer fab can promote on-time deliveries. One type of critical fab equipment is a diffusion oven which processes multiple wafer lots (jobs) simultaneously in batches. We present a new polynomial time Batch Improvement Algorithm for scheduling a batch-processing machine to maximize on-time delivery performance (minimize total weighted tardiness) when job arrivals are dynamic. The proposed algorithm's performance is compared to previous research efforts under varying problem conditions. Experimental studies demonstrate the effectiveness of the Batch Improvement Algorithm.

Keywords:

• Heuristics
• Batch-processing
• Scheduling
• Semiconductor manufacturing