Crosstalk Analysis of Current-Mode Signalling-Coupled RLC Interconnects Using FDTD Technique

ABSTRACT

In nanometre regimes, interconnect crosstalk noise has serious implications as it affects the signal integrity of the system. An accurate analysis of crosstalk effects is very essential and a critical issue. This paper efficiently models and analyses the crosstalk effects in current-mode signalling (CMS) multiline-coupled-distributed resistance-inductance-capacitance (RLC) interconnects. The interconnects are driven by complementary metal-oxide-semiconductor (CMOS) gates. The non-linear behaviour of metal-oxide-semiconductor (MOS) transistors in CMOS gate is characterized by an nth power law model. Both inductive and capacitive couplings have been considered to incorporate coupling effects in interconnects. The model is formulated using a finite-difference time-domain (FDTD) technique. The functional and dynamic crosstalk effects have been analysed for different interconnect lengths and varying transition time for the first time in CMS interconnects. The efficacy of CMS interconnects is evaluated by comparison with the conventional voltage-mode signalling (VMS) interconnects. It is analysed that CMS interconnects have lesser crosstalk-induced delay than VMS interconnects. Also, normalized undershoot voltage in CMS interconnects is lesser as compared to VMS signalling interconnects. The results are validated using simulation program with integrated circuit emphasis simulations. The analyses have been carried out for 32 nm technology node.

KEYWORDS:

• Crosstalk
• current-mode signalling
• delay
• finite-difference time-domain (FDTD)
• on-chip interconnects, signal integrity
• voltage-mode signalling

Additional information

Notes on contributors

Yash Agrawal

Yash Agrawal received the BE degree in electronics and communication engineering from the Kavikulguru Institute of Technology and Science, Ramtek, Maharashtra, in 2009 and the MTech degree in VLSI design automation and techniques from the National Institute of Technology, Hamirpur, Himachal Pradesh, India, in 2012. He is currently working towards the PhD degree from the National Institute of Technology, Hamirpur, Himachal Pradesh. His current research interests include design techniques and modelling of high speed on-chip VLSI interconnects. He achieved university rank during his bachelor's degree. He achieved the third place in all India Mentor Graphics design contest held at Bangalore, India, in 2011. He has been the chairman and awarded with the best forum member of IETE Students' Forum at KITS Ramtek, Nagpur Division during 2008–2009. He has also been awarded first rank in many national and inter-college level paper presentations.

E-mail: [email protected]

Rajeevan Chandel

Rajeevan Chandel received the BE degree in electronics and communication engineering from TIET now Thapar University Patiala, India, in 1990. She is a double gold medallist of Himachal Pradesh University, Shimla, India, in Pre-University and Pre-Engineering in 1985 and 1986, respectively. She received the MTech degree in integrated electronics and circuits from the Indian Institute of Technology (IIT), Delhi, India, in 1997. She was awarded the PhD degree from IIT Roorkee, India, under QIP scheme of Government of India in 2005. She joined the Department of Electronics and Communication Engineering, NIT Hamirpur, HP India, as a lecturer in 1990, where presently she is working as a professor and has been the head of the department twice. She has five MHRD, MCIT sponsored projects to her credit from the Governmemt of India. She has over 50 research papers in international and national journals of repute and over 75 in conferences. Her research interest includes electronics circuit modelling and low-power VLSI design. She is a fellow of IETE(I), life member of ISTE(I), and member of IEEE.

E-mail: [email protected]