Stability Analysis in Top-Contact and Side-Contact Graphene Nanoribbon Interconnects

ABSTRACT

In this paper, we have analysed the relative stability of copper, top-contact (TC) and side-contact (SC) multilayer graphene nanoribbon (MLGNR)-based interconnects for next-generation VLSI interconnect technology. We have analysed the Bode stability by varying the interconnect length (10–100 µm) at 16 nm ITRS technology node. Similar analysis has been performed by varying the interconnect width (11–22 nm) at 10 µm interconnect length. It is observed that by increasing the interconnect length (l) as well as interconnect width (w), the relative stability increases for three different types of interconnects. Our analysis shows that the copper-based interconnect shows more stability due to high gain margin and phase margin for a wide range of interconnect length (10–100 µm) as compared to the TC-GNR and SC-GNR interconnect systems. It is also observed that by increasing the wire width, the gain and phase margin of TC-GNR is higher than copper and SC-GNR interconnect. Our analysis predicts that the TC-GNR is the best candidate for interconnect modelling in terms of stability across different technology nodes considering the other benefits of TC-GNR as compared with copper and SC-GNR.

KEYWORDS:

• Single-layer GNR (SLGNR)
• Multilayer GNR (MLGNR)
• TC–GNR
• SC–GNR
• Mean free path (MFP)
• Stability
• Bode
• Interconnect

Additional information

Funding

This work is partially supported by the DIT, Government of West Bengal, India under VLSI Design Project.

Notes on contributors

Sandip Bhattacharya

Sandip Bhattacharya was born in Pandaveswar, Burdwan, West Bengal, India, on 21 July 1983. He received the BE degree in electronics and communication engineering from University Institute of Technology, University of Burdwan, India, in 2006, and the MTech degree in electronics and communication engineering (embedded systems) from Moulana Abul Kalam Ajad Technical University (formerly West Bengal University of Technology), India, in 2011. He is currently working towards the PhD degree at the School of VLSI Technology, Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University), Shibpur, Howrah, India.

E-mail: [email protected]

Debaprasad Das

Debaprasad Das (M’12) was born in Haria, Purba Medinipur, West Bengal, India, on 10 May 1975. He received the BSc (Hons.) degree in physics from Vidyasagar University, Midnapore, India, in 1995; the BTech degree in radiophysics and electronics from University of Calcutta, Kolkata, India, in 1998; the ME degree in electronics and telecommunication engineering from the Jadavpur University, Kolkata, in 2006; and PhD degree at the School of VLSI Technology from Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University), Shibpur, Howrah, India in 2013. From 1998 to 2003, he was a senior engineer at the ASIC Product Development Centre, Texas Instruments, Bangalore, India. From 2003 to 2013, he was an assistant professor in Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India. He joined the Department of Electronics and Communication Engineering, Assam Central University, Assam, India, in 2013, where he is currently a full professor. He has authored or co-authored several research papers in national and international conferences and journals. He is also the author of the book VLSI Design (New Delhi, India: Oxford University Press, 2010), and co-authored the book Carbon Nanotube and GNR Interconnect (Taylor & Francis, USA: CRC Press, 2014). His research interests include VLSI design, developing of electronic design automation tools for interconnect modelling, analysing crosstalk and reliability, digital CMOS logic design, and modelling of nanoelectronic devices and interconnects.

E-mail: [email protected]

Hafizur Rahaman

Hafizur Rahaman (SM’10) received the BE degree in electrical engineering from the Bengal Engineering College, Calcutta University, Kolkata, India, in 1986; the ME degree in electrical engineering; and the PhD degree in computer science and engineering, both from the Jadavpur University, Kolkata, in 1988 and 2003, respectively. From 1995 to 2003, he was a faculty member at the Indian Institute of Information Technology, Calcutta. Since 2003, he has been a faculty member of the Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University), Shibpur, India, where he is currently a full professor. He has contributed to VLSI computer-aided design and test, as well as to fault-tolerant computing, design and test of microfluidic biochips and emerging nanotechnologies with major publications in journals and conferences, spanning more than 15 years. He has published more than 120 research articles in archival journals and refereed conference proceedings. Dr Rahaman visited as a post-doctoral research fellow under EPSARC Grant at the Department of Computer Science, Bristol University, Bristol, UK, during 2006–2007. During 2008–2009, on the basis of his research contributions, he received the Royal Society International Fellowship Award to carry out advanced research in the Design and Verification Division of Computer Science Department, University of Bristol. He leads the VLSI design and test group at the Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University), Shibpur. He is the principal coordinator of the Department of Information Technology, Ministry of Communication and Information Technology; Government of India funded SMDP (special manpower development in VLSI design and related software) Research Project at Indian Institute of Engineering Science and Technology (formerly Bengal Engineering and Science University). He also received grant of Rs 164 lacs for establishing VLSI Design Centre at Bengal Engineering and Science University. He is a member of the VLSI Society of India (VSI), the IEEE Computer Society, and ACM Sigda. He served on the conference committees of the International Conference on VLSI Design, the VLSI Design and Test Workshop (VDAT), the Asian Test Symposium (2005), and the International Symposium on Electronic System Design (ISED) (2010–2014).

E-mail: [email protected], [email protected]