Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm

ABSTRACT

The quest for low power increases with the advancement in technology as a result of continuous device scaling. Static random access memory (SRAM) represents the technology workhorse due to its compatibility with the logic. Denser SRAM is required for modern high performance applications. The stability of SRAM in low power regime needs attention due to increasing effects of process variations in low dimensions. These variations are steep for the scaled devices. Data retention voltage (DRV) is the main parameter for SRAM to estimate the cell stability. This paper analyses the stability of SRAM in terms of process corner analysis of DRV. The process corner analysis in addition to temperature analysis is carried out with the Cadence Virtuoso tool using the 45 nm generic process design kit (GPDK) technology file. At lower temperature, the DRV is lowest at the FF process corner and highest at the SS corner. But for higher temperature, the highest value of DRV is obtained at the SF corner. Similarly, with varying cell ratio (CR), the process corner analysis shows that FF and TT are the best corners for low power operations.

KEYWORDS:

• Data retention
• DRV
• Low power
• Process corners
• SRAM
• Temperature variations

ACKNOWLEDGMENTS

One of the author (Ruchi) wishes to acknowledge the QIP Programme for supporting her PhD.

DISCLOSURE STATEMENT

No potential conflict of interest was reported by the authors.

Additional information

Notes on contributors

Ruchi Gupta

Ruchi Gupta (S’13) received the MSc and MTech degrees in Electronics (Microelectronics and VLSI Design) from the Kurukshetra University, Kurukshetra, India, in 2004 and 2006 respectively. She is pursuing PhD degree from IIT Roorkee. From 2007 to 2014, she was with Kurukshetra University as an assistant professor. Her current research interests include ultra-low power design, digital design, and low power memory design.

E-mail: [email protected]

S. Dasgupta

S. Dasgupta (M’14) received the PhD degree from IIT-BHU Varanasi, India, in 2000. He is currently an associate professor with the Electronics and Communication Engineering Department, IIT Roorkee, Roorkee, India. His current research interests include ultra-low power memory design, novel semiconductor device modelling, and radiation effects on ICs.

E-mail: [email protected]